31
TITLE: Architecture for Transparent Binary Acceleration of Loops with Memory Accesses  Full Text
AUTHORS: Nuno Paulino ; Joao Canas Ferreira ; Joao M P Cardoso ;
PUBLISHED: 2013, SOURCE: 9th International Applied Reconfigurable Computing Symposium (ARC) in RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS, VOLUME: 7806
INDEXED IN: Scopus WOS DBLP CrossRef: 2
32
TITLE: Transparent runtime migration of loop-based traces of processor instructions to reconfigurable processing units  Full Text
AUTHORS: Bispo, J ; Paulino, N ; Cardoso, JMP ; Ferreira, JC ;
PUBLISHED: 2013, SOURCE: International Journal of Reconfigurable Computing, VOLUME: 2013
INDEXED IN: Scopus DBLP CrossRef: 6
33
TITLE: Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
AUTHORS: Joao Bispo ; Nuno Paulino ; Joao M P Cardoso ; Joao C Ferreira ;
PUBLISHED: 2013, SOURCE: IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOLUME: 9, ISSUE: 3
INDEXED IN: Scopus WOS DBLP CrossRef: 10
34
TITLE: From Instruction Traces to Specialized Reconfigurable Arrays
AUTHORS: João Bispo ; Nuno Miguel Cardanha Paulino ; João M P Cardoso ; João Canas Ferreira ;
PUBLISHED: 2011, SOURCE: 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011 in 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011
INDEXED IN: Scopus DBLP CrossRef: 6
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