João Paulo de Castro Canas Ferreira


AuthID: R-000-7A5

Confirmed Publications: 95



71
TITLE: Creation of Partial FPGA Configurations at Run-Time
AUTHORS: Miguel L Silva; Joao Canas Ferreira ;
PUBLISHED: 2010, SOURCE: 13th Euromicro Conference on Digital System Design on Architectures, Methods and Tools in 13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS
INDEXED IN: Scopus WOS DBLP CrossRef: 4
IN MY: ORCID | ResearcherID | DBLP
72
TITLE: Erlang Inspired Hardware
AUTHORS: Paulo Ferreira ; João Canas Ferreira ; José Carlos Alves ;
PUBLISHED: 2010, SOURCE: 20th International Conference on Field Programmable Logic and Applications, FPL 2010 in International Conference on Field Programmable Logic and Applications, FPL 2010, August 31 2010 - September 2, 2010, Milano, Italy
INDEXED IN: Scopus DBLP CrossRef
IN MY: ORCID | ResearcherID | DBLP
73
TITLE: FPGA-based real-time disparity computation and object location
AUTHORS: Santos, PM ; Ferreira, JC ;
PUBLISHED: 2010, SOURCE: 28th Norchip Conference, NORCHIP 2010 in 28th Norchip Conference, NORCHIP 2010
INDEXED IN: Scopus CrossRef: 3
IN MY: ORCID | ResearcherID
74
TITLE: FPGA-based rectification of stereo images
AUTHORS: João G P Rodrigues; João Canas Ferreira ;
PUBLISHED: 2010, SOURCE: 2010 Conference on Design and Architectures for Signal and Image Processing, DASIP2010 in Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, DASIP 2010, Edinburgh, Scotland, UK, October 26-28, 2010, Electronic Chips & Systems design Initiative, ECSI
INDEXED IN: Scopus DBLP CrossRef: 6
IN MY: ORCID | DBLP
75
TITLE: Run-time Generation of Partial Configurations for Arithmetic Expressions  Full Text
AUTHORS: Miguel L Silva; Joao Canas Ferreira ;
PUBLISHED: 2010, SOURCE: 53rd Midwest Symposium on Circuits and Systems (MWSCAS 2010) in 53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | ResearcherID
76
TITLE: Non-Rectangular Reconfigurable Cores for System-on-Chip
AUTHORS: Pedro Alves; Joao Canas Ferreira ;
PUBLISHED: 2009, SOURCE: Conference on VLSI Circuits and Systems IV in VLSI CIRCUITS AND SYSTEMS IV, VOLUME: 7363
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | ResearcherID
77
TITLE: GENERATION OF PARTIAL FPGA CONFIGURATIONS AT RUN-TIME
AUTHORS: Miguel L Silva; Joao Canas Ferreira ;
PUBLISHED: 2008, SOURCE: International Conference on Field Programmable and Logic Applications in 2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2
INDEXED IN: Scopus WOS DBLP CrossRef: 15
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78
TITLE: Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems  Full Text
AUTHORS: Silva, ML; Ferreira, JC ;
PUBLISHED: 2007, SOURCE: 20th International Conference on Design of Ciruits and Integrated Systems in IET COMPUTERS AND DIGITAL TECHNIQUES, VOLUME: 1, ISSUE: 5
INDEXED IN: Scopus WOS DBLP CrossRef: 7
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79
TITLE: Exploiting dynamic reconfiguration of platform FPGAs: implementation issues
AUTHORS: Silva, ML; João Canas Ferreira ;
PUBLISHED: 2006, SOURCE: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, VOLUME: 2006
INDEXED IN: Scopus DBLP CrossRef: 3
IN MY: ORCID | ResearcherID | DBLP
80
TITLE: Support for partial run-time reconfiguration of platform FPGAs  Full Text
AUTHORS: Miguel L Silva; Joao Canas Ferreira ;
PUBLISHED: 2006, SOURCE: JOURNAL OF SYSTEMS ARCHITECTURE, VOLUME: 52, ISSUE: 12
INDEXED IN: Scopus WOS DBLP CrossRef: 20
IN MY: ORCID | ResearcherID | DBLP
Página 8 de 10. Total de resultados: 95.

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