Mário Pereira Véstias


AuthID: R-000-CZ3

Confirmed Publications: 130



111
TITLE: A dynamic buffer resize technique for networks-on-chip on FPGA
AUTHORS: Vestias, MP ; Neto, HC ;
PUBLISHED: 2011, SOURCE: 2011 7th Southern Conference on Programmable Logic, SPL 2011 in Proceedings of the 2011 7th Southern Conference on Programmable Logic, SPL 2011
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
112
TITLE: Iterative decimal multiplication using binary arithmetic
AUTHORS: Vestias, MP ; Neto, HC ;
PUBLISHED: 2011, SOURCE: 2011 7th Southern Conference on Programmable Logic, SPL 2011 in Proceedings of the 2011 7th Southern Conference on Programmable Logic, SPL 2011
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
113
TITLE: Revisiting the Newton-Raphson iterative method for decimal division
AUTHORS: Vestias, MP ; Neto, HC ;
PUBLISHED: 2011, SOURCE: 21st International Conference on Field Programmable Logic and Applications, FPL 2011 in Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
114
TITLE: A DCM Demapper for MB-OFDM on FPGA
AUTHORS: Mario Vestias ; Hugo Santos; Helena Sarmento ;
PUBLISHED: 2010, SOURCE: IEEE International Conference on Consumer Electronics in 2010 DIGEST OF TECHNICAL PAPERS INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS ICCE
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
115
TITLE: Implementing and testing the FPGA prototype of a DCM demodulator using the Matlab/Simulink environment
AUTHORS: Hugo Santos; Mario Vestias ; Helena Sarmento;
PUBLISHED: 2010, SOURCE: 1st IEEE Latin American Symposium on Circuits and Systems (LASCAS) in 2010 FIRST IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS)
INDEXED IN: WOS
IN MY: ORCID | CIÊNCIAVITAE
116
TITLE: Parallel decimal multipliers using binary multipliers
AUTHORS: Vestias, MP ; Neto, HC ;
PUBLISHED: 2010, SOURCE: 6th Southern Programmable Logic Conference, SPL 2010 in 6th Southern Programmable Logic Conference, SPL 2010 - Proceedings
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
117
TITLE: Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs
AUTHORS: Rui Duarte; Horacio Neto ; Mario Vestias ;
PUBLISHED: 2009, SOURCE: 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools in PROCEEDINGS OF THE 2009 12TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, ARCHITECTURES, METHODS AND TOOLS
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
118
TITLE: Run-Time Reconfigurable Array using Magnetic RAM
AUTHORS: Victor Silva; Luis B Oliveira ; Jorge R Fernandes ; Mario P Vestias ; Horacio C Neto ;
PUBLISHED: 2009, SOURCE: 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools in PROCEEDINGS OF THE 2009 12TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, ARCHITECTURES, METHODS AND TOOLS
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
119
TITLE: Architectural tradeoffs in the design of barrel shifters for reconfigurable computing
AUTHORS: Horacio C Neto ; Mario P Vestias ;
PUBLISHED: 2008, SOURCE: 4th Southern Conference on Programmable Logic in 2008 4TH SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
120
TITLE: DECIMAL MULTIPLIER ON FPGA USING EMBEDDED BINARY MULTIPLIERS
AUTHORS: Horacio C Neto ; Mario R Vestias ;
PUBLISHED: 2008, SOURCE: 18th International Conference on Field Programmable and Logic Applications in 2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
Page 12 of 13. Total results: 130.

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