Mário Pereira Véstias


AuthID: R-000-CZ3

Confirmed Publications: 122



21
TITLE: Convolutional Neural Network
AUTHORS: Mário Pereira Véstias ;
PUBLISHED: 2021, SOURCE: Advances in Information Quality and Management - Encyclopedia of Information Science and Technology, Fifth Edition
INDEXED IN: CrossRef: 6
IN MY: ORCID | CIÊNCIAVITAE
22
TITLE: Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor  Full Text
AUTHORS: Vestias, MP ; Neto, HC;
PUBLISHED: 2021, SOURCE: ALGORITHMS, VOLUME: 14, ISSUE: 7
INDEXED IN: WOS CrossRef: 2
IN MY: ORCID | CIÊNCIAVITAE
23
TITLE: IOb-Cache: A High-Performance Configurable Open-Source Cache
AUTHORS: Roque, JV; Lopes, JD; Vestias, MP ; de Sousa, JT;
PUBLISHED: 2021, SOURCE: ALGORITHMS, VOLUME: 14, ISSUE: 8
INDEXED IN: WOS CrossRef: 3 Handle
IN MY: ORCID | CIÊNCIAVITAE
24
TITLE: A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs
AUTHORS: Vestias, MP ; Duarte, RP; De Sousa, JT; Neto, HC;
PUBLISHED: 2020, SOURCE: IEEE ACCESS, VOLUME: 8
INDEXED IN: Scopus WOS CrossRef: 11
IN MY: ORCID | CIÊNCIAVITAE
25
TITLE: A fast and scalable architecture to run convolutional neural networks in low density FPGAs  Full Text
AUTHORS: Véstias, MP ; Duarte, RP; de Sousa, JT; Neto, HC;
PUBLISHED: 2020, SOURCE: Microprocessors and Microsystems, VOLUME: 77
INDEXED IN: Scopus CrossRef: 21
IN MY: ORCID | CIÊNCIAVITAE
26
TITLE: A fast and scalable architecture to run convolutional neural networks in low density FPGAs  Full Text
AUTHORS: Vestias, MP ; Duarte, RP; de Sousa, JT; Neto, HC;
PUBLISHED: 2020, SOURCE: MICROPROCESSORS AND MICROSYSTEMS, VOLUME: 77
INDEXED IN: WOS
IN MY: ORCID | CIÊNCIAVITAE
27
TITLE: Deep Learning on Edge. Challenges and Trends
AUTHORS: Mário P Véstias ;
PUBLISHED: 2020, SOURCE: Advances in Computational Intelligence and Robotics - Smart Systems Design, Applications, and Challenges
INDEXED IN: CrossRef: 8
IN MY: ORCID | CIÊNCIAVITAE
28
TITLE: Efficient Design of Pruned Convolutional Neural Networks on FPGA  Full Text
AUTHORS: Mario Vestias ;
PUBLISHED: 2020, SOURCE: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
INDEXED IN: WOS
IN MY: ORCID | CIÊNCIAVITAE
29
TITLE: Efficient Design of Pruned Convolutional Neural Networks on FPGA
AUTHORS: Véstias, M ;
PUBLISHED: 2020, SOURCE: Journal of Signal Processing Systems, VOLUME: 93, ISSUE: 5
INDEXED IN: Scopus CrossRef: 10
IN MY: ORCID | CIÊNCIAVITAE
30
TITLE: Field-Programmable Gate Array
AUTHORS: Véstias, MP ;
PUBLISHED: 2020, SOURCE: Encyclopedia of Information Science and Technology, Fifth Edition
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
Page 3 of 13. Total results: 122.

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