Paulo Ferreira Godinho Flores


AuthID: R-000-EBX

Confirmed Publications: 79



41
TITLE: An efficient low power multiple-value look-up table targeting quaternary FPGAs
AUTHORS: Lazzari, C; Fernandes, J; Flores, P ; Monteiro, J;
PUBLISHED: 2011, SOURCE: 20th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2010 in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), VOLUME: 6448 LNCS
INDEXED IN: Scopus
IN MY: ORCID | CIÊNCIAVITAE
42
TITLE: An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs
AUTHORS: Lazzari, C; Fernandes, J ; Flores, P ; Monteiro, J ;
PUBLISHED: 2011, SOURCE: 20th International Workshop on Power and Timing Modeling, Optimization and Simulation in INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, VOLUME: 6448
INDEXED IN: Scopus WOS CrossRef: 6
IN MY: ORCID | CIÊNCIAVITAE
43
TITLE: Design of low-power multiple constant multiplications using low-complexity minimum depth operations
AUTHORS: Aksoy, L ; Costa, E; Flores, P ; Monteiro, J ;
PUBLISHED: 2011, SOURCE: 21st Great Lakes Symposium on VLSI, GLSVLSI 2011 in Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
44
TITLE: Efficient shift-adds design of digit-serial multiple constant multiplications
AUTHORS: Aksoy, L ; Lazzari, C; Costa, E; Flores, P ; Monteiro, J ;
PUBLISHED: 2011, SOURCE: 21st Great Lakes Symposium on VLSI, GLSVLSI 2011 in Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
45
TITLE: Finding the optimal tradeoff between area and delay in multiple constant multiplications  Full Text
AUTHORS: Aksoy, L ; Costa, E; Flores, P ; Monteiro, J ;
PUBLISHED: 2011, SOURCE: MICROPROCESSORS AND MICROSYSTEMS, VOLUME: 35, ISSUE: 8
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | ResearcherID | CIÊNCIAVITAE
46
TITLE: Low power Multiple-value voltage-mode look-Up table for quaternary field programmable gate arrays
AUTHORS: Lazzari, C; Fernandes, J ; Flores, P ; Monteiro, J ;
PUBLISHED: 2011, SOURCE: Journal of Low Power Electronics, VOLUME: 7, ISSUE: 2
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
47
TITLE: Optimization of Area in Digit-Serial Multiple Constant Multiplications at Gate-Level
AUTHORS: Aksoy, L ; Lazzari, C; Costa, E; Flores, P ; Monteiro, J ;
PUBLISHED: 2011, SOURCE: IEEE International Symposium on Circuits and Systems (ISCAS) in 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
48
TITLE: Optimization of gate-level area in high throughput multiple constant multiplications
AUTHORS: Aksoy, L ; Costa, E; Flores, P ; Monteiro, J ;
PUBLISHED: 2011, SOURCE: 2011 20th European Conference on Circuit Theory and Design, ECCTD 2011 in 2011 20th European Conference on Circuit Theory and Design, ECCTD 2011
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
49
TITLE: A new quaternary FPGA based on a voltage-mode multi-valued circuit
AUTHORS: Lazzari, C; Flores, P ; Monteiro, J ; Carro, L;
PUBLISHED: 2010, SOURCE: Design, Automation and Test in Europe Conference and Exhibition, DATE 2010 in Proceedings -Design, Automation and Test in Europe, DATE
INDEXED IN: Scopus
IN MY: ORCID | CIÊNCIAVITAE
50
TITLE: Design of Low-Complexity and High-Speed Digital Finite Impulse Response Filters
AUTHORS: Diego Jaccottet; Eduardo Costa; Levent Aksoy ; Paulo Flores ; Jose Monteiro ;
PUBLISHED: 2010, SOURCE: 18th IEEE/IFIP International Conference on VLSI and System-on-Chip in PROCEEDINGS OF THE 2010 18TH IEEE/IFIP INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | ResearcherID | CIÊNCIAVITAE
Page 5 of 8. Total results: 79.

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