João Manuel Paiva Cardoso


AuthID: R-000-75E

Confirmed Publications: 272



261
TITLE: Loop dissevering: A technique for temporally partitioning loops in dynamically reconfigurable computing platforms
AUTHORS: Cardoso, JMP ;
PUBLISHED: 2003, SOURCE: International Parallel and Distributed Processing Symposium, IPDPS 2003 in Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003
INDEXED IN: Scopus DBLP CrossRef: 5
IN MY: ORCID | DBLP | CIÊNCIAVITAE
262
TITLE: On combining temporal partitioning and sharing of functional units in compilation for reconfigurable architectures
AUTHORS: Cardoso, JMP ;
PUBLISHED: 2003, SOURCE: IEEE TRANSACTIONS ON COMPUTERS, VOLUME: 52, ISSUE: 10
INDEXED IN: Scopus WOS DBLP CrossRef: 40
IN MY: ORCID | ResearcherID | DBLP | CIÊNCIAVITAE
263
TITLE: Fast and guaranteed C compilation onto the PACT-XPP™ reconfigurable computing platform
AUTHORS: Cardoso, JMP ; Weinhardt, M;
PUBLISHED: 2002, SOURCE: 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines in 10TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS, VOLUME: 2002-January
INDEXED IN: Scopus WOS DBLP CrossRef: 4
IN MY: ORCID | DBLP
264
TITLE: XPP-VC: A C Compiler with temporal partitioning for the PACT-XPP architecture
AUTHORS: Cardoso, JMP ; Weinhardt, M;
PUBLISHED: 2002, SOURCE: 12th International Conference on Field-Programmable Logic and Applications in FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLUME: 2438
INDEXED IN: Scopus WOS DBLP CrossRef: 16
IN MY: ORCID | DBLP
265
266
TITLE: Novel Algorithm Combining Temporal Partitioning and Sharing of Functional Units
AUTHORS: Cardoso, JMP ;
PUBLISHED: 2001, SOURCE: 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2001 in Proceedings - 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2001
INDEXED IN: Scopus DBLP
IN MY: ORCID | DBLP | CIÊNCIAVITAE
267
TITLE: An enhanced static-list scheduling algorithm for temporal partitioning onto RPUs
AUTHORS: Cardoso, JMP ; Neto, HC;
PUBLISHED: 2000, SOURCE: IFIP 10th International Conference on Very Large Scale Integration (VLSI 99) in VLSI: SYSTEMS ON A CHIP, VOLUME: 34
INDEXED IN: WOS DBLP CrossRef: 10
IN MY: ORCID | DBLP
268
TITLE: Architectures and compilers to support reconfigurable computing  Full Text
AUTHORS: João M P Cardoso ; Mário P Vestístias;
PUBLISHED: 1999, SOURCE: XRDS, VOLUME: 5, ISSUE: 3
INDEXED IN: DBLP CrossRef: 2
IN MY: ORCID | DBLP
269
TITLE: Fast hardware compilation of behaviors into an FPGA-based dynamic reconfigurable computing system
AUTHORS: Joéo M P Cardoso ; Horácio C Neto;
PUBLISHED: 1999, SOURCE: Proceedings - 12th Symposium on Integrated Circuits and Systems Design, SBCCI 1999
INDEXED IN: Scopus CrossRef: 3
IN MY: ORCID | CIÊNCIAVITAE
270
Page 27 of 28. Total results: 272.

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