Jorge Manuel dos Santos Ribeiro Fernandes


AuthID: R-000-7S7

Confirmed Publications: 131



41
TITLE: Quaternary logic lookup table in standard CMOS
AUTHORS: Brito, D; Rabuske, TG; Fernandes, JR ; Flores, P; Monteiro, J;
PUBLISHED: 2015, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, ISSUE: 2
INDEXED IN: Scopus
IN MY: ORCID | CIÊNCIAVITAE
42
TITLE: Quaternary Logic Lookup Table in Standard CMOS  Full Text
AUTHORS: Brito, D; Rabuske, TG; Fernandes, JR ; Flores, P ; Monteiro, J ;
PUBLISHED: 2015, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 23, ISSUE: 2
INDEXED IN: Scopus WOS CrossRef: 10
IN MY: ORCID | CIÊNCIAVITAE
43
TITLE: A sub-ranging 2-Step 7-bit self-calibrated comparator-based binary-search ADC
AUTHORS: Rabuske, F; Rabuske, T; Fernandes, J ;
PUBLISHED: 2014, SOURCE: 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 in Proceedings - IEEE International Symposium on Circuits and Systems
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
44
TITLE: An Efficient RF Power Harvester for Low Input Power with Reduced Dead-zone
AUTHORS: Hugo Goncalves; Jorge Fernandes ; Taimur Rabuske; Miguel Martins;
PUBLISHED: 2014, SOURCE: IEEE International Symposium on Circuits and Systems (ISCAS) in 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
45
TITLE: Experimental Evaluation of Wide Range Injection Locking in a CMOS RC Oscillator
AUTHORS: Ortigueira, E; Oliveira, LB; Fernandes, JR ; Silva, MM;
PUBLISHED: 2014, SOURCE: IEEE International Symposium on Circuits and Systems (ISCAS) in 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
46
TITLE: Noise-aware simulation-based sizing and optimization of clocked comparators  Full Text
AUTHORS: Taimur Rabuske; Jorge Fernandes ;
PUBLISHED: 2014, SOURCE: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, VOLUME: 81, ISSUE: 3
INDEXED IN: Scopus WOS
IN MY: ORCID | CIÊNCIAVITAE
47
TITLE: Noise-aware simulation-based sizing and optimization of clocked comparators  Full Text
AUTHORS: Rabuske, T; Fernandes, J ;
PUBLISHED: 2014, SOURCE: Analog Integrated Circuits and Signal Processing, VOLUME: 81, ISSUE: 3
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
48
TITLE: A 5-bit 1.5GSps Calibration-less Binary Search ADC Using Threshold Reconfigurable Comparators
AUTHORS: Taimur Rabuske; Fabio Rabuske; Jorge Fernandes ; Cesar Rodrigues;
PUBLISHED: 2013, SOURCE: IEEE International Symposium on Circuits and Systems (ISCAS) in 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
49
TITLE: A reconfigurable computing architecture using magnetic tunneling junction memories
AUTHORS: Silva, V; Fernandes, J ; Vestias, M ; Neto, H;
PUBLISHED: 2013, SOURCE: 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 in 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
50
TITLE: A Self-Calibrated 10-bit 1 MSps SAR ADC with Reduced-Voltage Charge-Sharing DAC
AUTHORS: Taimur Rabuske; Jorge Fernandes ; Fabio Rabuske; Cesar Rodrigues; Marcelino B dos Santos ;
PUBLISHED: 2013, SOURCE: IEEE International Symposium on Circuits and Systems (ISCAS) in 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
Page 5 of 14. Total results: 131.

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