José Carlos Alves Pereira Monteiro


AuthID: R-000-85F

Confirmed Publications: 98



91
TITLE: Techniques for power estimation and optimization at the logic level: A survey  Full Text
AUTHORS: Monteiro, J ; Devadas, S;
PUBLISHED: 1996, SOURCE: JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, VOLUME: 13, ISSUE: 2-3
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | ResearcherID
92
TITLE: POWER ESTIMATION METHODS FOR SEQUENTIAL LOGIC-CIRCUITS  Full Text
AUTHORS: TSUI, CY; MONTEIRO, J ; PEDRAM, M; DEVADAS, S; DESPAIN, AM; LIN, B;
PUBLISHED: 1995, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 3, ISSUE: 3
INDEXED IN: Scopus WOS
IN MY: ResearcherID
93
TITLE: Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs
AUTHORS: Jose Monteiro ; Srinivas Devadas;
PUBLISHED: 1995, SOURCE: Proceedings of the 1995 International Symposium on Low Power Design in Proceedings of the International Symposium on Low Power Design
INDEXED IN: Scopus
IN MY: ORCID
94
TITLE: Bitwise encoding of finite state machines
AUTHORS: Jose Monteiro ; James Kukula; Srinivas Devadas; Horacio Neto;
PUBLISHED: 1994, SOURCE: Proceedings of the 7th International Conference on VLSI Design in Proceedings of the IEEE International Conference on VLSI Design
INDEXED IN: Scopus
IN MY: ORCID
95
TITLE: Methodology for efficient estimation of switching activity in sequential logic circuits  Full Text
AUTHORS: Jose Monteiro ; Srinivas Devadas; Bill Lin;
PUBLISHED: 1994, SOURCE: Proceedings of the 31st Design Automation Conference in Proceedings - Design Automation Conference
INDEXED IN: Scopus
IN MY: ORCID
96
TITLE: Precomputation-based sequential logic optimization for low power  Full Text
AUTHORS: Mazhar Alidina; Jose Monteiro ; Srinivas Devadas; Abhijit Ghosh; Marios Papaefthymiou;
PUBLISHED: 1994, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 2, ISSUE: 4
INDEXED IN: Scopus CrossRef
IN MY: ORCID
97
TITLE: PRECOMPUTATION-BASED SEQUENTIAL LOGIC OPTIMIZATION FOR LOW POWER  Full Text
AUTHORS: ALIDINA, M; MONTEIRO, J ; DEVADAS, S; GHOSH, A; PAPAEFTHYMIOU, M;
PUBLISHED: 1994, SOURCE: 1994 IEEE/ACM International Conference on Computer-Aided Design in 1994 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS
INDEXED IN: Scopus WOS
IN MY: ResearcherID
98
TITLE: RETIMING SEQUENTIAL-CIRCUITS FOR LOW-POWER
AUTHORS: MONTEIRO, J ; DEVADAS, S; GHOSH, A;
PUBLISHED: 1993, SOURCE: 1993 IEEE/ACM International Conference on Computer-Aided Design in 1993 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS, VOLUME: 07, ISSUE: 02
INDEXED IN: Scopus WOS CrossRef: 3
IN MY: ORCID
Page 10 of 10. Total results: 98.

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