José Carlos Alves Pereira Monteiro


AuthID: R-000-85F

Confirmed Publications: 134



101
TITLE: Low Power Architectures for FFT and FIR Dedicated Datapaths
AUTHORS: Costa, E; Bampi, S; Monteiro, J ;
PUBLISHED: 2003, SOURCE: 46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003 in Midwest Symposium on Circuits and Systems, VOLUME: 3
INDEXED IN: Scopus CrossRef: 1
IN MY: ORCID | CIÊNCIAVITAE
102
TITLE: A new architecture for 2's complement Gray encoded array multiplier
AUTHORS: Costa, E; Bampi, S; Monteiro, J ;
PUBLISHED: 2002, SOURCE: 15th Symposium on Integrated Circuits and Systems Design in 15TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS
INDEXED IN: WOS CrossRef: 7
IN MY: ORCID | CIÊNCIAVITAE
103
TITLE: A new architecture for signed Radix-2(m) pure array multipliers  Full Text
AUTHORS: Costa, E; Bampi, S; Monteiro, J ;
PUBLISHED: 2002, SOURCE: 20th IEEE International Conference on Computer Design in ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | ResearcherID | CIÊNCIAVITAE
104
TITLE: Implicit FSM decomposition applied to low-power design  Full Text
AUTHORS: Monteiro, JC ; Oliveira, AL ;
PUBLISHED: 2002, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 10, ISSUE: 5
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | ResearcherID | CIÊNCIAVITAE
105
TITLE: Optimization of combinational and sequential logic circuits for low power using precomputation
AUTHORS: Monteiro, J ; Rinderknecht, J; Devadas, S; Ghosh, A;
PUBLISHED: 2002, SOURCE: Proceedings Sixteenth Conference on Advanced Research in VLSI
INDEXED IN: CrossRef: 15
IN MY: ORCID | CIÊNCIAVITAE
106
TITLE: Probabilistic bottom-up RTL power estimation
AUTHORS: Ferreira, R; A.-M Trullemans; Costa, J; Monteiro, J ;
PUBLISHED: 2002, SOURCE: Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)
INDEXED IN: CrossRef
IN MY: ORCID | CIÊNCIAVITAE
107
TITLE: Retiming sequential circuits for low power
AUTHORS: Monteiro, J ; Devadas, S; Ghosh, A;
PUBLISHED: 2002, SOURCE: Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)
INDEXED IN: CrossRef: 92
IN MY: ORCID | CIÊNCIAVITAE
108
TITLE: Power efficient arithmetic operand encoding
AUTHORS: Costa, E; Bampi, S; Monteiro, J ;
PUBLISHED: 2001, SOURCE: 14th Symposium on Integrated Circuits and Systems Design in 14TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS
INDEXED IN: WOS
IN MY: ResearcherID
109
TITLE: Power efficient arithmetic operand encoding [CMOS circuits]
AUTHORS: Costa, E; Bampi, S; Monteiro, J ;
PUBLISHED: 2001, SOURCE: 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001 in Proceedings - 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
110
TITLE: Power optimized Viterbi decoder implementation through architectural transforms
AUTHORS: Portela, J; Monteiro, J ;
PUBLISHED: 2001, SOURCE: 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001 in Proceedings - 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
Page 11 of 14. Total results: 134.

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