José Carlos Alves Pereira Monteiro


AuthID: R-000-85F

Confirmed Publications: 134



111
TITLE: Power optimized Viterbi Decoder implementation throught architectural transforms
AUTHORS: Portela, J; Monteiro, J ;
PUBLISHED: 2001, SOURCE: 14th Symposium on Integrated Circuits and Systems Design in 14TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS
INDEXED IN: WOS
IN MY: ResearcherID
112
TITLE: FSM decomposition by direct circuit manipulation applied to low power design
AUTHORS: Monteiro, JC ; Oliveira, AL ;
PUBLISHED: 2000, SOURCE: 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000 in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
INDEXED IN: Scopus DBLP CrossRef
IN MY: ORCID | CIÊNCIAVITAE
113
TITLE: Integrating dynamic power management in the design flow
AUTHORS: Mota, A; Ferreira, N; Oliveira, A ; Monteiro, J ;
PUBLISHED: 2000, SOURCE: IFIP 10th International Conference on Very Large Scale Integration (VLSI 99) in VLSI: SYSTEMS ON A CHIP, VOLUME: 34
INDEXED IN: WOS DBLP
114
TITLE: Observability analysis of embedded software for coverage-directed validation
AUTHORS: Costa, JC; Devadas, S; Monteiro, JC ;
PUBLISHED: 2000, SOURCE: IEEE/ACM International Conference on Computer Aided Design (ICCAD-2000) in ICCAD - 2000 : IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
115
TITLE: A probabilistic approach for RT-level power modeling
AUTHORS: Costa, J; Monteiro, J ; Silveira, L. Miguel ; Devadas, S;
PUBLISHED: 1999, SOURCE: 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999 in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, VOLUME: 2
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
116
TITLE: Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation
AUTHORS: Flores, P ; Costa, J; Neto, H ; Monteiro, J ; Marques Silva, J ;
PUBLISHED: 1999, SOURCE: 12th International Conference on VLSI Design in TWELFTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS
INDEXED IN: Scopus WOS DBLP CrossRef: 30 Unpaywall
IN MY: ORCID | ResearcherID | CIÊNCIAVITAE
117
TITLE: Finite state machine decomposition for low power  Full Text
AUTHORS: Monteiro, JC ; Oliveira, AL ;
PUBLISHED: 1998, SOURCE: 35th Design Automation Conference in 1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | ResearcherID | CIÊNCIAVITAE
118
TITLE: Power estimation under user-specified input sequences and programs  Full Text
AUTHORS: Monteiro, J ; Devadas, S;
PUBLISHED: 1998, SOURCE: INTEGRATED COMPUTER-AIDED ENGINEERING, VOLUME: 5, ISSUE: 2
INDEXED IN: Scopus WOS
IN MY: ORCID | ResearcherID | CIÊNCIAVITAE
119
TITLE: Power optimization of combinational modules using self-timed precomputation
AUTHORS: Mota, A; Monteiro, J ; Oliveira, A ;
PUBLISHED: 1998, SOURCE: IEEE International Symposium on Circuits and Systems (ISCAS 98) in ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6, VOLUME: 2
INDEXED IN: Scopus WOS
IN MY: ORCID | ResearcherID | CIÊNCIAVITAE
120
TITLE: Sequential logic optimization for low power using input-disabling precomputation architectures  Full Text
AUTHORS: Monteiro, J ; Devadas, S; Ghosh, A;
PUBLISHED: 1998, SOURCE: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOLUME: 17, ISSUE: 3
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | ResearcherID | CIÊNCIAVITAE
Page 12 of 14. Total results: 134.

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