ProfileOfResearchers

122

TITLE: Estimation of average switching activity in combinational logic circuits using symbolic simulation Full Text
AUTHORS: Monteiro, J ; Devadas, S; Ghosh, A; Keutzer, K; White, J;
PUBLISHED: 1997, SOURCE: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOLUME: 16, ISSUE: 1

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123

TITLE: Switching activity estimation using limited depth reconvergent path analysis
AUTHORS: Costa, JC; Monteiro, JC ; Devadas, S;
PUBLISHED: 1997, SOURCE: 1997 International Symposium on Low Power Electronics and Design in 1997 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, PROCEEDINGS

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124

TITLE: Power estimation methods for sequential logic circuits (vol 3, pg 404, 1995) Full Text
AUTHORS: Tsui, CY; Monteiro, J ; Pedram, M; Devadas, S; Despain, AM; Lin, B;
PUBLISHED: 1996, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 4, ISSUE: 4

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125

TITLE: Scheduling techniques to enable power management Full Text
AUTHORS: Monteiro, J ; Devadas, S; Ashar, P; Mauskar, A;
PUBLISHED: 1996, SOURCE: 33rd Design Automation Conference in 33RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 1996

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126

TITLE: Techniques for power estimation and optimization at the logic level: A survey Full Text
AUTHORS: Monteiro, J ; Devadas, S;
PUBLISHED: 1996, SOURCE: JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, VOLUME: 13, ISSUE: 2-3

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127

TITLE: Power estimation methods for sequential logic circuits Full Text
AUTHORS: Chi-Ying Tsui, ; Monteiro, J ; Massoud Pedram, ; Srinivas Devadas, ; A.M Despain; Lin, B;
PUBLISHED: 1995, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems - IEEE Trans. VLSI Syst., VOLUME: 3, ISSUE: 3

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128

TITLE: POWER ESTIMATION METHODS FOR SEQUENTIAL LOGIC-CIRCUITS Full Text
AUTHORS: TSUI, CY; MONTEIRO, J ; PEDRAM, M; DEVADAS, S; DESPAIN, AM; LIN, B;
PUBLISHED: 1995, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 3, ISSUE: 3

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129

TITLE: Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs
AUTHORS: Jose Monteiro ; Srinivas Devadas;
PUBLISHED: 1995, SOURCE: Proceedings of the 1995 International Symposium on Low Power Design in Proceedings of the International Symposium on Low Power Design

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130

TITLE: Bitwise encoding of finite state machines
AUTHORS: Jose Monteiro ; James Kukula; Srinivas Devadas; Horacio Neto;
PUBLISHED: 1994, SOURCE: Proceedings of the 7th International Conference on VLSI Design in Proceedings of the IEEE International Conference on VLSI Design

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