José Carlos Alves Pereira Monteiro


AuthID: R-000-85F

Confirmed Publications: 134



71
TITLE: Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications
AUTHORS: Aksoy, L ; Costa, E; Flores, P ; Monteiro, J ;
PUBLISHED: 2010, SOURCE: 13th Euromicro Conference on Digital System Design on Architectures, Methods and Tools in 13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS
INDEXED IN: Scopus WOS
72
TITLE: Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications
AUTHORS: Levent Aksoy; Eduardo Costa; Paulo Flores ; Jose Monteiro ;
PUBLISHED: 2010, SOURCE: 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
INDEXED IN: CrossRef
IN MY: ORCID | CIÊNCIAVITAE
73
TITLE: Radix-2 Decimation in Time (DIT) FFT implementation based on a matrix-multiple constant multiplication approach
AUTHORS: Ghissoni, S; Costa, E; Lazzari, C; Monteiro, J ; Aksoy, L ; Reis, R;
PUBLISHED: 2010, SOURCE: 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 in 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
74
TITLE: Voltage-mode Quaternary FPGAs: An Evaluation of Interconnections
AUTHORS: Cristiano Lazzari; Paulo Flores ; Jose Monteiro ; Luigi Carro;
PUBLISHED: 2010, SOURCE: International Symposium on Circuits and Systems Nano-Bio Circuit Fabrics and Systems (ISCAS 2010) in 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
75
TITLE: A MILP-based Approach to Path Sensitization of Embedded Software
AUTHORS: Costa, JC; Monteiro, JC ;
PUBLISHED: 2009, SOURCE: Design, Automation and Test in Europe Conference and Exhibition in DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
76
TITLE: Generating Worst-Case Stimuli for Accurate Power Grid Analysis
AUTHORS: Pedro Marques Morgado; Paulo F Flores ; Jose C Monteiro ; Silveira, L. Miguel ;
PUBLISHED: 2009, SOURCE: 18th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) in INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, VOLUME: 5349
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
77
TITLE: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
AUTHORS: Lars Svensson; José Monteiro ;
PUBLISHED: 2009, SOURCE: Lecture Notes in Computer Science
INDEXED IN: CrossRef
IN MY: ORCID | CIÊNCIAVITAE
78
TITLE: Parameter Timing in SVM-Based Power Macro-Modeling
AUTHORS: Antonio Gusmao; Silveira, L. Miguel ; Jose Monteiro ;
PUBLISHED: 2009, SOURCE: 10th International Symposium on Quality Electronic Design in ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
79
TITLE: Power and Delay Comparison of Binary and Quaternary Arithmetic Circuits
AUTHORS: Cristiano Lazzari; Paulo Flores ; Jose Carlos Monteiro ;
PUBLISHED: 2009, SOURCE: 3rd International Conference on Signals, Circuits and Systems in 2009 3RD INTERNATIONAL CONFERENCE ON SIGNALS, CIRCUITS AND SYSTEMS (SCS 2009)
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
80
TITLE: Computation of the minimal set of paths for observability-based statement coverage
AUTHORS: Costa, J; Monteiro, J ;
PUBLISHED: 2008, SOURCE: 15th International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES 2008 in Proceedings of The 15th International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2008
INDEXED IN: Scopus
IN MY: ORCID | CIÊNCIAVITAE
Page 8 of 14. Total results: 134.

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