Leonel Augusto Pires Seabra Sousa


AuthID: R-000-93B

Confirmed Publications: 370



121
TITLE: Stream-based parallel computing methodology and development environment for high performance manycore accelerators
AUTHORS: Yamagiwa, S; Falcao, G ; Wada, K; Sousa, L ;
PUBLISHED: 2015, SOURCE: Horizons in Computer Science Research, VOLUME: 11
INDEXED IN: Scopus
IN MY: ORCID | CIÊNCIAVITAE
122
TITLE: Stretching the limits of Programmable Embedded Devices for Public-key Cryptography
AUTHORS: Paulo Martins; Leonel Sousa ;
PUBLISHED: 2015, SOURCE: CS2@HiPEAC, VOLUME: 2015-January
INDEXED IN: Scopus DBLP CrossRef: 4
IN MY: ORCID
123
TITLE: TOWARDS GPU HEVC INTRA DECODING: SEIZING FINE-GRAIN PARALLELISM
AUTHORS: de Souza, DF; Ilic, A; Roma, N ; Sousa, L ;
PUBLISHED: 2015, SOURCE: IEEE International Conference on Multimedia & Expo (ICME) in 2015 IEEE INTERNATIONAL CONFERENCE ON MULTIMEDIA & EXPO (ICME), VOLUME: 2015-August
INDEXED IN: Scopus WOS DBLP CrossRef: 8
IN MY: ORCID
124
TITLE: A Flexible Architecture for Modular Arithmetic Hardware Accelerators based on RNS  Full Text
AUTHORS: Antao, S; Sousa, L ;
PUBLISHED: 2014, SOURCE: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, VOLUME: 76, ISSUE: 3
INDEXED IN: WOS DBLP CrossRef: 2
IN MY: ORCID
125
TITLE: Accelerating Phylogenetic Inference on GPUs: an OpenACC and CUDA comparison
AUTHORS: Kuan, L; Neves, J; Pratas, F; Tomás, P; Sousa, L ;
PUBLISHED: 2014, SOURCE: 2nd International Work-Conference on Bioinformatics and Biomedical Engineering (IWBBIO) in PROCEEDINGS IWBBIO 2014: INTERNATIONAL WORK-CONFERENCE ON BIOINFORMATICS AND BIOMEDICAL ENGINEERING, VOLS 1 AND 2
INDEXED IN: WOS DBLP
126
TITLE: An Efficient Scalable RNS Architecture for Large Dynamic Ranges  Full Text
AUTHORS: Matutino, PM; Chaves, R ; Sousa, L ;
PUBLISHED: 2014, SOURCE: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, VOLUME: 77, ISSUE: 1-2
INDEXED IN: Scopus WOS DBLP CrossRef: 8
IN MY: ORCID
127
TITLE: Arithmetic-Based Binary-to-RNS Converter Modulo {2n ±k} for jn-Bit Dynamic Range  Full Text
AUTHORS: Matutino, PM; Chaves, R ; Sousa, L ;
PUBLISHED: 2014, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, ISSUE: 3
INDEXED IN: Scopus CrossRef: 8
IN MY: ORCID | CIÊNCIAVITAE
128
TITLE: Cache-aware Roofline model: Upgrading the loft  Full Text
AUTHORS: Aleksandar Ilic ; Frederico Pratas; Leonel Sousa ;
PUBLISHED: 2014, SOURCE: IEEE COMPUTER ARCHITECTURE LETTERS, VOLUME: 13, ISSUE: 1
INDEXED IN: Scopus WOS
129
TITLE: Cache-aware Roofline model: Upgrading the loft
AUTHORS: Aleksandar Ilic ; Frederico Pratas; Leonel Sousa ;
PUBLISHED: 2014, SOURCE: IEEE Comput. Archit. Lett., VOLUME: 13, ISSUE: 1
INDEXED IN: Scopus DBLP CrossRef: 106
IN MY: ORCID
130
TITLE: COLLABORATIVE INTER-PREDICTION ON CPU plus GPU SYSTEMS  Full Text
AUTHORS: Momcilovic, S; Ilic, A; Roma, N ; Sousa, L ;
PUBLISHED: 2014, SOURCE: IEEE International Conference on Image Processing (ICIP) in 2014 IEEE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING (ICIP)
INDEXED IN: Scopus WOS DBLP CrossRef: 2
IN MY: ORCID
Page 13 of 37. Total results: 370.

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