151
TITLE: On the Evaluation of Multi-core Systems with SIMD Engines for Public-Key Cryptography  Full Text
AUTHORS: Paulo Martins; Leonel Sousa ;
PUBLISHED: 2014, SOURCE: 26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshops, SBAC-PADW 2014 in 26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshop, SBAC-PAD Workshop 2014, Paris, France, October 22-24, 2014, VOLUME: 22-24-October-2014
INDEXED IN: Scopus DBLP CrossRef
152
TITLE: OPENCL PARALLELIZATION OF THE HEVC DE-QUANTIZATION AND INVERSE TRANSFORM FOR HETEROGENEOUS PLATFORMS
AUTHORS: Diego F de Souza; Nuno Roma ; Leonel Sousa ;
PUBLISHED: 2014, SOURCE: 22nd European Signal Processing Conference (EUSIPCO) in 2014 PROCEEDINGS OF THE 22ND EUROPEAN SIGNAL PROCESSING CONFERENCE (EUSIPCO)
INDEXED IN: Scopus WOS DBLP
153
TITLE: Performance-aware task management and frequency scaling in embedded systems  Full Text
AUTHORS: Gaspar, F; Ilic, A; Tomas, P ; Sousa, L ;
PUBLISHED: 2014, SOURCE: 26th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2014 in Proceedings - Symposium on Computer Architecture and High Performance Computing
INDEXED IN: Scopus DBLP CrossRef: 2
154
TITLE: Reconfigurable data flow engine for HEVC motion estimation
AUTHORS: Thomas D'huys; Svetislav Momcilovic; Frederico Pratas; Leonel Sousa ;
PUBLISHED: 2014, SOURCE: 2014 IEEE International Conference on Image Processing (ICIP)
INDEXED IN: CrossRef
155
TITLE: Reconfigurable data flow engine for HEVC motion estimation
AUTHORS: Thomas D'huys; Svetislav Momcilovic; Frederico Pratas; Leonel Sousa ;
PUBLISHED: 2014, SOURCE: 2014 IEEE International Conference on Image Processing, ICIP 2014, Paris, France, October 27-30, 2014
INDEXED IN: Scopus DBLP
156
TITLE: Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations  Full Text
AUTHORS: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L ;
PUBLISHED: 2014, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, ISSUE: 2
INDEXED IN: Scopus CrossRef: 15
157
TITLE: SchedMon: A Performance and Energy Monitoring Tool for Modern Multi-cores
AUTHORS: Luis Tanica; Aleksandar Ilic; Pedro Tomas ; Leonel Sousa ;
PUBLISHED: 2014, SOURCE: 20th Euro-Par International Workshops in EURO-PAR 2014: PARALLEL PROCESSING WORKSHOPS, PT II, VOLUME: 8806
INDEXED IN: Scopus WOS DBLP CrossRef: 7
158
TITLE: Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs  Full Text
AUTHORS: Tiago Dias; Nuno Roma ; Leonel Sousa ;
PUBLISHED: 2014, SOURCE: EURASIP JOURNAL ON ADVANCES IN SIGNAL PROCESSING, VOLUME: 2014, ISSUE: 1
INDEXED IN: Scopus WOS DBLP CrossRef
159
TITLE: A Compact and Scalable RNS Architecture  Full Text
AUTHORS: Pedro Miguens Matutino; Ricardo Chaves ; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP) in PROCEEDINGS OF THE 2013 IEEE 24TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 13)
INDEXED IN: Scopus WOS DBLP CrossRef
160
TITLE: A comparison of computing architectures and parallelization frameworks based on a two-dimensional FDTD
AUTHORS: Kuan, L; Tomas, P ; Sousa, L ;
PUBLISHED: 2013, SOURCE: 2013 11th International Conference on High Performance Computing and Simulation, HPCS 2013 in Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013
INDEXED IN: Scopus DBLP CrossRef: 2
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