Leonel Augusto Pires Seabra Sousa


AuthID: R-000-93B

Confirmed Publications: 370



161
TITLE: Multi-level Parallelization of Advanced Video Coding on Hybrid CPU plus GPU Platforms
AUTHORS: Svetislav Momcilovic; Nuno Roma ; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: 18th International Conference on Euro-Par Parallel Processing in EURO-PAR 2012: PARALLEL PROCESSING WORKSHOPS, VOLUME: 7640
INDEXED IN: WOS
162
TITLE: On the Design of RNS Reverse Converters for the Four-Moduli Set {2<i><SUP>n</SUP></i>+1, 2<i><SUP>n</SUP></i>-1, 2<i><SUP>n</SUP></i>, 2<SUP><i>n</i>+1</SUP>+1}  Full Text
AUTHORS: Sousa, L ; Antao, S; Chaves, R ;
PUBLISHED: 2013, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 21, ISSUE: 10
INDEXED IN: Scopus WOS DBLP CrossRef: 25
IN MY: ORCID
163
TITLE: Open the Gates: Using High-level Synthesis Towards Programmable LDPC Decoders on FPGAs
AUTHORS: Pratas, F; Andrade, J; Falcao, G ; Silva, V; Sousa, L ;
PUBLISHED: 2013, SOURCE: IEEE Global Conference on Signal and Information Processing (GlobalSIP) in 2013 IEEE GLOBAL CONFERENCE ON SIGNAL AND INFORMATION PROCESSING (GLOBALSIP)
INDEXED IN: Scopus WOS DBLP CrossRef: 10
IN MY: ORCID
164
TITLE: Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks
AUTHORS: Ambrose, JA; Pettenghi, H ; Jayasinghe, D; Sousa, L ;
PUBLISHED: 2013, SOURCE: IET CIRCUITS DEVICES & SYSTEMS, VOLUME: 7, ISSUE: 5
INDEXED IN: Scopus WOS DBLP CrossRef: 5
165
TITLE: RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to (8<i>n</i>+1)-bit
AUTHORS: Pettenghi, H ; Chaves, R ; Sousa, L ;
PUBLISHED: 2013, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, VOLUME: 60, ISSUE: 6
INDEXED IN: Scopus WOS DBLP CrossRef: 38
IN MY: ORCID
166
TITLE: Scalable Unified Transform Architecture for Advanced Video Coding Embedded Systems  Full Text
AUTHORS: Dias, T; López, S; Roma, N ; Sousa, L ;
PUBLISHED: 2013, SOURCE: INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, VOLUME: 41, ISSUE: 2
INDEXED IN: Scopus WOS DBLP CrossRef: 1
IN MY: ORCID
167
TITLE: Stressing the BER simulation of LDPC codes in the error floor region using GPU clusters
AUTHORS: Falcao, G ; Andrade, J; Silva, V; Yamagiwa, S; Sousa, L ;
PUBLISHED: 2013, SOURCE: 10th IEEE International Symposium on Wireless Communication Systems 2013, ISWCS 2013 in Proceedings of the International Symposium on Wireless Communication Systems
INDEXED IN: Scopus
IN MY: ORCID | CIÊNCIAVITAE
168
TITLE: Stressing the BER simulation of LDPC codes in the error floor region using GPU clusters
AUTHORS: Gabriel Falcão Paiva Fernandes; João Andrade; Vítor Manuel Mendes da Silva; Shinichi Yamagiwa; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: ISWCS
INDEXED IN: DBLP
169
TITLE: The CRNS Framework and its Application to Programmable and Reconfigurable Cryptography  Full Text
AUTHORS: Antao, S; Sousa, L ;
PUBLISHED: 2013, SOURCE: ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, VOLUME: 9, ISSUE: 4
INDEXED IN: Scopus WOS DBLP CrossRef: 20
IN MY: ORCID
170
TITLE: 2-Axis Magnetometers Based on Full Wheatstone Bridges Incorporating Magnetic Tunnel Junctions Connected in Series
AUTHORS: Ricardo Ferreira; Elvira Paz; Paulo P Freitas ; Joao Ribeiro; Jose Germano ; Leonel Sousa ;
PUBLISHED: 2012, SOURCE: International Magnetics Conference (INTERMAG) in IEEE TRANSACTIONS ON MAGNETICS, VOLUME: 48, ISSUE: 11
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | ResearcherID | CIÊNCIAVITAE
Page 17 of 37. Total results: 370.

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