Leonel Augusto Pires Seabra Sousa


AuthID: R-000-93B

Confirmed Publications: 387



161
TITLE: A Lab Project on the Design and Implementation of Programmable and Configurable Embedded Systems  Full Text
AUTHORS: Leonel Sousa ; Samuel Antao; Jose Germano ;
PUBLISHED: 2013, SOURCE: IEEE TRANSACTIONS ON EDUCATION, VOLUME: 56, ISSUE: 3
INDEXED IN: Scopus WOS DBLP CrossRef
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162
TITLE: Accelerating the Computation of Induced Dipoles for Molecular Mechanics with Dataflow Engines
AUTHORS: Frederico Pratas; Diego Oriato; Oliver Pell; Ricardo A Mata; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) in 2013 IEEE 21ST ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM)
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | DBLP | CIÊNCIAVITAE
163
TITLE: AN RNS-BASED ARCHITECTURE TARGETING HARDWARE ACCELERATORS FOR MODULAR ARITHMETIC
AUTHORS: Samuel Antao; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) in 2013 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP)
INDEXED IN: Scopus WOS DBLP CrossRef
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164
TITLE: DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks
AUTHORS: Ambrose, JA; Pettenghi, H ; Sousa, L ;
PUBLISHED: 2013, SOURCE: 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
INDEXED IN: Scopus DBLP CrossRef
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165
TITLE: High performance multi-standard architecture for DCT computation in H.264/AVC High Profile and HEVC codecs
AUTHORS: Dias, T; Roma, N ; Sousa, L ;
PUBLISHED: 2013, SOURCE: 2013 7th Conference on Design and Architectures for Signal and Image Processing, DASIP 2013 in Conference on Design and Architectures for Signal and Image Processing, DASIP
INDEXED IN: Scopus DBLP
IN MY: ORCID | DBLP | CIÊNCIAVITAE
166
TITLE: Method to Design General RNS Reverse Converters for Extended Moduli Sets
AUTHORS: Hector Pettenghi ; Ricardo Chaves ; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, VOLUME: 60, ISSUE: 12
INDEXED IN: Scopus WOS DBLP CrossRef
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167
TITLE: Monitoring Performance and Power for Application Characterization with the Cache-Aware Roofline Model
AUTHORS: Diogo Antão; Luís Taniça; Aleksandar Ilic; Frederico Pratas; Pedro Tomás ; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: Parallel Processing and Applied Mathematics - 10th International Conference, PPAM 2013, Warsaw, Poland, September 8-11, 2013, Revised Selected Papers, Part I, VOLUME: 8384
INDEXED IN: DBLP CrossRef: 4
IN MY: ORCID | DBLP | CIÊNCIAVITAE
168
TITLE: Multi-level Parallelization of Advanced Video Coding on Hybrid CPU plus GPU Platforms
AUTHORS: Svetislav Momcilovic; Nuno Roma ; Leonel Sousa ;
PUBLISHED: 2013, SOURCE: 18th International Conference on Euro-Par Parallel Processing in EURO-PAR 2012: PARALLEL PROCESSING WORKSHOPS, VOLUME: 7640
INDEXED IN: WOS
169
TITLE: On the Design of RNS Reverse Converters for the Four-Moduli Set {2(n)+1, 2(n)-1, 2(n), 2(n+1)+1}  Full Text
AUTHORS: Leonel Sousa ; Samuel Antao; Ricardo Chaves ;
PUBLISHED: 2013, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 21, ISSUE: 10
INDEXED IN: Scopus WOS DBLP CrossRef
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170
TITLE: Open the Gates: Using High-level Synthesis Towards Programmable LDPC Decoders on FPGAs
AUTHORS: Pratas, F; Andrade, J; Falcao, G ; Silva, V; Sousa, L ;
PUBLISHED: 2013, SOURCE: IEEE Global Conference on Signal and Information Processing (GlobalSIP) in 2013 IEEE GLOBAL CONFERENCE ON SIGNAL AND INFORMATION PROCESSING (GLOBALSIP)
INDEXED IN: Scopus WOS DBLP CrossRef
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Page 17 of 39. Total results: 387.

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