331
TITLE: Rescheduling for optimized SHA-1 calculation
AUTHORS: Ricardo Chaves ; Georgi Kuzmanov; Leonel Sousa ; Stamatis Vassiliadis;
PUBLISHED: 2006, SOURCE: 6th International Workshop on Embedded Computer Systems - Architectures, Modeling and Simulation in EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, PROCEEDINGS, VOLUME: 4017
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332
TITLE: Scalable magnetoresistive biochips for biomolecular recognition
AUTHORS: Cardoso, F ; Ferreira, H ; Freitas, P ; Conde, J ; Chu, V ; Germano, J ; Sousa, L ; Piedade, M ; Martins, V; Fonseca, L; Cabral, J ;
PUBLISHED: 2006, SOURCE: INTERMAG 2006 - IEEE International Magnetics Conference in INTERMAG 2006 - IEEE International Magnetics Conference
INDEXED IN: Scopus CrossRef
333
TITLE: Temperature modelling of a biochip for DNA analysis
AUTHORS: Costa, BA; Lemos, JM ; Piedade, MS ; Sousa, L ; Almeida, T ; Germano, J ; Freitas, P ; Feffeira, H ; Cardoso, F ;
PUBLISHED: 2006, SOURCE: 14th Mediterranean Conference on Control and Automation in Proceedings of 2006 Mediterranean Conference on Control and Automation, Vols 1 and 2
INDEXED IN: Scopus WOS CrossRef
334
TITLE: Toward a realistic task scheduling model  Full Text
AUTHORS: Sinnen, O; Sousa, LA ; Sandnes, FE;
PUBLISHED: 2006, SOURCE: IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOLUME: 17, ISSUE: 3
INDEXED IN: Scopus WOS DBLP CrossRef
335
TITLE: A universal architecture for designing efficient modulo 2(n)+1 multipliers (vol 52, pg 1166, 2005)
AUTHORS: Sousa, L ; Chaves, R ;
PUBLISHED: 2005, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, VOLUME: 52, ISSUE: 9
INDEXED IN: Scopus WOS DBLP CrossRef
336
TITLE: A universal architecture for designing efficient modulo 2(n),+1 multipliers
AUTHORS: Sousa, L ; Chaves, R ;
PUBLISHED: 2005, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, VOLUME: 52, ISSUE: 6
INDEXED IN: Scopus WOS DBLP CrossRef
337
TITLE: Bioinspired stimulus encoder for cortical visual neuroprostheses  Full Text
AUTHORS: Sousa, L ; Tomas, P ; Pelayo, F; Martinez, A; Morillas, CA; Romero, S;
PUBLISHED: 2005, SOURCE: New Algorithms, Architectures and Applications for Reconfigurable Computing
INDEXED IN: Scopus CrossRef: 2
338
TITLE: Communication contention in task scheduling  Full Text
AUTHORS: Sinnen, O; Sousa, LA ;
PUBLISHED: 2005, SOURCE: IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOLUME: 16, ISSUE: 6
INDEXED IN: Scopus WOS DBLP CrossRef
339
TITLE: Customizable and reduced hardware motion estimation processors  Full Text
AUTHORS: Roma, N ; Dias, T; Sousa, L ;
PUBLISHED: 2005, SOURCE: New Algorithms, Architectures and Applications for Reconfigurable Computing
INDEXED IN: Scopus CrossRef
340
TITLE: Efficient motion vector refinement architecture for sub-pixel motion estimation systems  Full Text
AUTHORS: Dias, T; Roma, N ; Sousa, L ;
PUBLISHED: 2005, SOURCE: IEEE Workshop on Signal Processing Systems Design and Implementations (SiPS 05) in 2005 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS - DESIGN AND IMPLEMENTATION (SIPS), VOLUME: 2005
INDEXED IN: Scopus WOS CrossRef
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