Luís Jorge Brás Monteiro Guerra e Silva


AuthID: R-000-9HS

Confirmed Publications: 14



11
TITLE: Solving satisfiability in combinational circuits  Full Text
AUTHORS: Marques Silva, J ; Silva, LGE ;
PUBLISHED: 2003, SOURCE: IEEE DESIGN & TEST OF COMPUTERS, VOLUME: 20, ISSUE: 4
INDEXED IN: Scopus WOS DBLP CrossRef: 10 Unpaywall
IN MY: ORCID | CIÊNCIAVITAE
12
TITLE: Satisfiability models and algorithms for circuit delay computation  Full Text
AUTHORS: Silva, LGE ; Marques Silva, J ; Silveira, L. Miguel ; Sakallah, KA;
PUBLISHED: 2002, SOURCE: ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, VOLUME: 7, ISSUE: 1
INDEXED IN: Scopus WOS DBLP CrossRef Unpaywall
IN MY: ORCID | CIÊNCIAVITAE
13
TITLE: Algorithms for solving Boolean Satisfiability in combinational circuits
AUTHORS: Silva, LGE ; Silveira, L. Miguel ; Marques Silva, J ;
PUBLISHED: 1999, SOURCE: Design, Automation and Test in Europe Conference and Exhibition in DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS
INDEXED IN: Scopus WOS DBLP CrossRef: 5
IN MY: CIÊNCIAVITAE
14
TITLE: Realistic delay modeling in satisfiability-based timing analysis
AUTHORS: Silva, LG ; Silva, JPM ; Silveira, L. Miguel ; Sakallah, KA;
PUBLISHED: 1998, SOURCE: IEEE International Symposium on Circuits and Systems (ISCAS 98) in ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6
INDEXED IN: WOS CrossRef: 8
IN MY: ORCID | CIÊNCIAVITAE
Page 2 of 2. Total results: 14.

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