Mário Pereira Véstias
AuthID: R-000-CZ3
1
TITLE: Fast and Accurate System for Onboard Target Recognition on Raw SAR Echo Data
AUTHORS: Gustavo Jacinto; Mário Véstias; Paulo Flores ; Rui Policarpo Duarte;
PUBLISHED: 2025
AUTHORS: Gustavo Jacinto; Mário Véstias; Paulo Flores ; Rui Policarpo Duarte;
PUBLISHED: 2025
2
TITLE: Enhancing Airport Traffic Flow: Intelligent System Based on VLC, Rerouting Techniques, and Adaptive Reward Learning Full Text
AUTHORS: Vieira, Manuela; Vieira, Manuel Augusto; Galvao, Goncalo; Louro, Paula; Fantoni, Alessandro; Vieira, Pedro; Vestias, Mario;
PUBLISHED: 2025, SOURCE: SENSORS, VOLUME: 25, ISSUE: 9
AUTHORS: Vieira, Manuela; Vieira, Manuel Augusto; Galvao, Goncalo; Louro, Paula; Fantoni, Alessandro; Vieira, Pedro; Vestias, Mario;
PUBLISHED: 2025, SOURCE: SENSORS, VOLUME: 25, ISSUE: 9
3
TITLE: PT-Float: A Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes
AUTHORS: de Sousa, Jose T.; Lopes, Joao D.; Serodio, Micaela; Neto, Horacio C.; Vestias, Mario P.;
PUBLISHED: 2024, SOURCE: 31st Symposium on Computer Arithmetic (ARITH) in PROCEEDINGS 2024 IEEE 31ST SYMPOSIUM ON COMPUTER ARITHMETIC, ARITH 2024
AUTHORS: de Sousa, Jose T.; Lopes, Joao D.; Serodio, Micaela; Neto, Horacio C.; Vestias, Mario P.;
PUBLISHED: 2024, SOURCE: 31st Symposium on Computer Arithmetic (ARITH) in PROCEEDINGS 2024 IEEE 31ST SYMPOSIUM ON COMPUTER ARITHMETIC, ARITH 2024
INDEXED IN: 
Scopus 
WOS
Scopus WOS4
TITLE: High-Performance Embedded System for Onboard Object Detection in Hyperspectral Images
AUTHORS: Mário Véstias; José Nascimento;
PUBLISHED: 2024, SOURCE: Artificial Intelligence and Image and Signal Processing for Remote Sensing XXX 2024 in Proceedings of SPIE - The International Society for Optical Engineering, VOLUME: 13196
AUTHORS: Mário Véstias; José Nascimento;
PUBLISHED: 2024, SOURCE: Artificial Intelligence and Image and Signal Processing for Remote Sensing XXX 2024 in Proceedings of SPIE - The International Society for Optical Engineering, VOLUME: 13196
INDEXED IN: Scopus
Scopus5
TITLE: Decimal multiplication in FPGA with a novel decimal adder/subtractor
AUTHORS: Mário Véstias; Horácio C Neto;
PUBLISHED: 2021, SOURCE: Algorithms, VOLUME: 14, ISSUE: 7
AUTHORS: Mário Véstias; Horácio C Neto;
PUBLISHED: 2021, SOURCE: Algorithms, VOLUME: 14, ISSUE: 7
INDEXED IN: 
Handle
Handle6
TITLE: Stochastic theater: stochastic datapath generation framework for fault-tolerant IoT sensors
AUTHORS: Rui P Duarte; Mário Véstias; Carlos Carvalho; João Casaleiro;
PUBLISHED: 2018, SOURCE: i-ETC: ISEL Academic Journal of Electronics, Telecommunications and Computers, VOLUME: 4, ISSUE: 1
AUTHORS: Rui P Duarte; Mário Véstias; Carlos Carvalho; João Casaleiro;
PUBLISHED: 2018, SOURCE: i-ETC: ISEL Academic Journal of Electronics, Telecommunications and Computers, VOLUME: 4, ISSUE: 1
INDEXED IN: Handle
Handle7
TITLE: A many-core overlay for high performance embedded computing on FPGAS
AUTHORS: Mário Véstias; Horácio Neto;
PUBLISHED: 2014, SOURCE: 1st International Workshop on FPGAs for Software Programmers (FSP 2014)
AUTHORS: Mário Véstias; Horácio Neto;
PUBLISHED: 2014, SOURCE: 1st International Workshop on FPGAs for Software Programmers (FSP 2014)
INDEXED IN: Handle
Handle8
TITLE: Decimal division using the newton-raphson method and radix-1000 arithmetic
AUTHORS: Vestias, MP; Neto, HC;
PUBLISHED: 2013, SOURCE: Embedded Systems Design with FPGAs
AUTHORS: Vestias, MP; Neto, HC;
PUBLISHED: 2013, SOURCE: Embedded Systems Design with FPGAs
INDEXED IN: Scopus
Scopus9
TITLE: Decimal Division Using the Newton–Raphson Method and Radix-1000 Arithmetic
AUTHORS: Mário P Véstias; Horácio C Neto;
PUBLISHED: 2012, SOURCE: Embedded Systems Design with FPGAs
AUTHORS: Mário P Véstias; Horácio C Neto;
PUBLISHED: 2012, SOURCE: Embedded Systems Design with FPGAs
INDEXED IN: 
CrossRef
CrossRef10
TITLE: Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers
AUTHORS: Mário P Véstias; Horácio C Neto;
PUBLISHED: 2010, SOURCE: Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication
AUTHORS: Mário P Véstias; Horácio C Neto;
PUBLISHED: 2010, SOURCE: Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication
INDEXED IN: CrossRef
CrossRef