Mário Pereira Véstias
AuthID: R-000-CZ3
91
TITLE: Decimal division using the newton-raphson method and radix-1000 arithmetic
AUTHORS: Vestias, MP; Neto, HC;
PUBLISHED: 2013, SOURCE: Embedded Systems Design with FPGAs
AUTHORS: Vestias, MP; Neto, HC;
PUBLISHED: 2013, SOURCE: Embedded Systems Design with FPGAs
INDEXED IN: 
Scopus
Scopus92
TITLE: Very low resource table-based FPGA evaluation of elementary functions
AUTHORS: Horacio C Neto; Mario P Vestias;
PUBLISHED: 2013, SOURCE: International Conference on Reconfigurable Computing and FPGAs (ReConFig) in 2013 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG)
AUTHORS: Horacio C Neto; Mario P Vestias;
PUBLISHED: 2013, SOURCE: International Conference on Reconfigurable Computing and FPGAs (ReConFig) in 2013 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG)
INDEXED IN: 
WOS
WOS IN MY: 
ORCID
ORCID93
TITLE: ANALYSIS OF MATRIX MULTIPLICATION ON HIGH DENSITY VIRTEX-7 FPGA
AUTHORS: Wilson Jose; Ana Rita Silva; Horacio Neto; Mario Vestias;
PUBLISHED: 2013, SOURCE: 23rd International Conference on Field Programmable Logic and Applications (FPL) in 2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS
AUTHORS: Wilson Jose; Ana Rita Silva; Horacio Neto; Mario Vestias;
PUBLISHED: 2013, SOURCE: 23rd International Conference on Field Programmable Logic and Applications (FPL) in 2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS
INDEXED IN: WOS
WOS IN MY: ORCID
ORCID94
TITLE: A RECONFIGURABLE COMPUTING ARCHITECTURE USING MAGNETIC TUNNELING JUNCTION MEMORIES
AUTHORS: Victor Silva; Jorge Fernandes; Mario Vestias; Horacio Neto;
PUBLISHED: 2013, SOURCE: 23rd International Conference on Field Programmable Logic and Applications (FPL) in 2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS
AUTHORS: Victor Silva; Jorge Fernandes; Mario Vestias; Horacio Neto;
PUBLISHED: 2013, SOURCE: 23rd International Conference on Field Programmable Logic and Applications (FPL) in 2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS
INDEXED IN: WOS
WOS IN MY: ORCID
ORCID95
TITLE: Decimal Division Using the Newton–Raphson Method and Radix-1000 Arithmetic
AUTHORS: Mário P Véstias; Horácio C Neto;
PUBLISHED: 2012, SOURCE: Embedded Systems Design with FPGAs
AUTHORS: Mário P Véstias; Horácio C Neto;
PUBLISHED: 2012, SOURCE: Embedded Systems Design with FPGAs
INDEXED IN: 
CrossRef
CrossRef96
TITLE: Non-Volane Memory Circuits for FIMS and TAS Writing Techniques on Magnetic Tunnelling Junctions
AUTHORS: Victor Silva; Mario P Vestias; Horacio C Neto; Jorge R Fernandes;
PUBLISHED: 2012, SOURCE: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
AUTHORS: Victor Silva; Mario P Vestias; Horacio C Neto; Jorge R Fernandes;
PUBLISHED: 2012, SOURCE: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
INDEXED IN: WOS
WOS IN MY: ORCID
ORCID97
TITLE: FPGA Implementation of IEEE 802.15.3c Receiver
AUTHORS: Véstias, M; Sarmento, H;
PUBLISHED: 2012, SOURCE: 2012 IEEE 16TH INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS (ISCE)
AUTHORS: Véstias, M; Sarmento, H;
PUBLISHED: 2012, SOURCE: 2012 IEEE 16TH INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS (ISCE)
INDEXED IN: WOS 
Handle
WOS Handle IN MY: ORCID
ORCID98
TITLE: Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers
AUTHORS: Mário P Véstias; Horácio C Neto;
PUBLISHED: 2010, SOURCE: Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication
AUTHORS: Mário P Véstias; Horácio C Neto;
PUBLISHED: 2010, SOURCE: Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication
INDEXED IN: CrossRef
CrossRef99
TITLE: Implementing and testing the FPGA prototype of a DCM demodulator using the Matlab/Simulink environment
AUTHORS: Hugo Santos; Mario Vestias; Helena Sarmento;
PUBLISHED: 2010, SOURCE: 1st IEEE Latin American Symposium on Circuits and Systems (LASCAS) in 2010 FIRST IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS)
AUTHORS: Hugo Santos; Mario Vestias; Helena Sarmento;
PUBLISHED: 2010, SOURCE: 1st IEEE Latin American Symposium on Circuits and Systems (LASCAS) in 2010 FIRST IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS)
INDEXED IN: WOS
WOS IN MY: ORCID
ORCID100
TITLE: Area/performance improvement of NoC architectures
AUTHORS: Véstias, MP; Neto, HC;
PUBLISHED: 2006, SOURCE: RECONFIGURABLE COMPUTING: ARCHITECTURES AND APPLICATIONS, VOLUME: 3985
AUTHORS: Véstias, MP; Neto, HC;
PUBLISHED: 2006, SOURCE: RECONFIGURABLE COMPUTING: ARCHITECTURES AND APPLICATIONS, VOLUME: 3985
