Mário Pereira Véstias


AuthID: R-000-CZ3

Publications Requiring Validation

11
TITLE: A many-core overlay for high performance embedded computing on FPGAS
AUTHORS: Mário Véstias; Horácio Neto;
PUBLISHED: 2014, SOURCE: 1st International Workshop on FPGAs for Software Programmers (FSP 2014)
INDEXED IN: Handle
12
TITLE: Adaptive Network-on-Chip
AUTHORS: Mário Véstias; Horácio C Neto;
PUBLISHED: 2014, VOLUME: 8
INDEXED IN: Scopus
13
TITLE: Hardware Design for Decimal Multiplication
AUTHORS: Mário Véstias; Horácio C Neto;
PUBLISHED: 2014, VOLUME: 8
INDEXED IN: Scopus
14
TITLE: Decimal division using the newton-raphson method and radix-1000 arithmetic
AUTHORS: Vestias, MP; Neto, HC;
PUBLISHED: 2013, SOURCE: Embedded Systems Design with FPGAs
INDEXED IN: Scopus
15
TITLE: Decimal Division Using the Newton–Raphson Method and Radix-1000 Arithmetic
AUTHORS: Mário P Véstias; Horácio C Neto;
PUBLISHED: 2012, SOURCE: Embedded Systems Design with FPGAs
INDEXED IN: CrossRef
16
TITLE: Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers
AUTHORS: Mário P Véstias; Horácio C Neto;
PUBLISHED: 2010, SOURCE: Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication
INDEXED IN: CrossRef
17
Page 2 of 2. Total results: 17.

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