11
TITLE: A fast and scalable architecture to run convolutional neural networks in low density FPGAs
AUTHORS: Véstias, MP; Duarte, RP; de Sousa, JT; Neto, HC;
PUBLISHED: 2020, SOURCE: Microprocessors and Microsystems, VOLUME: 77
INDEXED IN: Scopus
12
TITLE: A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs
AUTHORS: Mario P Vestias; Rui P Duarte; Jose T De Sousa; Horacio C Neto;
PUBLISHED: 2020, SOURCE: IEEE ACCESS, VOLUME: 8
INDEXED IN: Scopus WOS
13
TITLE: Hyperspectral Compressive Sensing With a System-On-Chip FPGA
AUTHORS: Jose M P Nascimento; Mario P Vestias; Gabriel Martin;
PUBLISHED: 2020, SOURCE: IEEE JOURNAL OF SELECTED TOPICS IN APPLIED EARTH OBSERVATIONS AND REMOTE SENSING, VOLUME: 13
INDEXED IN: Scopus WOS
14
TITLE: Moving Deep Learning to the Edge  Full Text
AUTHORS: Mario P Vestias; Rui Policarpo Duarte; Jose T de Sousa; Horacio C Neto;
PUBLISHED: 2020, SOURCE: ALGORITHMS, VOLUME: 13, ISSUE: 5
INDEXED IN: WOS
15
TITLE: A fast and scalable architecture to run convolutional neural networks in low density FPGAs  Full Text
AUTHORS: Mario P Vestias; Rui P Duarte; Jose T de Sousa; Horacio C Neto;
PUBLISHED: 2020, SOURCE: MICROPROCESSORS AND MICROSYSTEMS, VOLUME: 77
INDEXED IN: WOS
16
TITLE: Stochastic Analyses on Relative Viscosity of Water-in-oil Emulsions
AUTHORS: Sousa, AM; Pereira, MJ; Matos, HA;
PUBLISHED: 2020, SOURCE: 30 European Symposium on Computer-Aided Process Engineering (ESCAPE) in 30TH EUROPEAN SYMPOSIUM ON COMPUTER AIDED PROCESS ENGINEERING, PTS A-C, VOLUME: 48
INDEXED IN: Scopus WOS
17
TITLE: Efficient Design of Pruned Convolutional Neural Networks on FPGA  Full Text
AUTHORS: Mario Vestias;
PUBLISHED: 2020, SOURCE: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
INDEXED IN: WOS
18
TITLE: A Survey of Convolutional Neural Networks on Edge with Reconfigurable Computing  Full Text
AUTHORS: Mario P Vestias;
PUBLISHED: 2019, SOURCE: ALGORITHMS, VOLUME: 12, ISSUE: 8
INDEXED IN: WOS
19
TITLE: Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores
AUTHORS: Luis Fiolhais; Fernando Goncalves; Rui P Duarte; Mario Vestias; Jose T de Sousa;
PUBLISHED: 2019, SOURCE: IEEE International Symposium on Circuits and Systems (IEEE ISCAS) in 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
INDEXED IN: WOS
20
TITLE: Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA
AUTHORS: Mario Vestias; Rui Policarpo Duarte; Jose T de Sousa; Horacio Neto;
PUBLISHED: 2019, SOURCE: 29th International Conference on Field-Programmable Logic and Applications (FPL) in 2019 29TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)
INDEXED IN: Scopus WOS
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