Nuno Filipe Silva Verissimo Paulino
AuthID: R-000-DNQ
101
TITLE: Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver
AUTHORS: Paulino, N; Serrazina, M; Goes, J ; Steiger Garcao, A ;
PUBLISHED: 2003, SOURCE: IEEE International Symposium on Circuits and Systems in PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING
AUTHORS: Paulino, N; Serrazina, M; Goes, J ; Steiger Garcao, A ;
PUBLISHED: 2003, SOURCE: IEEE International Symposium on Circuits and Systems in PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING
INDEXED IN: 
WOS
WOS IN MY: 
ORCID
ORCID102
TITLE: Design and optimization of low-voltage two-stage CMOS amplifiers with enhanced performance
AUTHORS: Tavares, R; Vaz, B; Goes, J ; Paulino, N; Steiger Garcao, A ;
PUBLISHED: 2003, SOURCE: IEEE International Symposium on Circuits and Systems in PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING, VOLUME: 1
AUTHORS: Tavares, R; Vaz, B; Goes, J ; Paulino, N; Steiger Garcao, A ;
PUBLISHED: 2003, SOURCE: IEEE International Symposium on Circuits and Systems in PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING, VOLUME: 1
103
TITLE: Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver
AUTHORS: Paulina, N; Serrazina, M; Goes, J ; Steiger Garcao, A ;
PUBLISHED: 2003, SOURCE: Proceedings of the 2003 IEEE International Symposium on Circuits and Systems in Proceedings - IEEE International Symposium on Circuits and Systems, VOLUME: 1
AUTHORS: Paulina, N; Serrazina, M; Goes, J ; Steiger Garcao, A ;
PUBLISHED: 2003, SOURCE: Proceedings of the 2003 IEEE International Symposium on Circuits and Systems in Proceedings - IEEE International Symposium on Circuits and Systems, VOLUME: 1
INDEXED IN: 
Scopus
Scopus104
TITLE: A 2.7 VCMOS IF transceiver for PHS application
AUTHORS: Yin, GH; Ahmed, K; Shamlou, D; Grilo, J; Law, S; Wong, C; Paulino, N;
PUBLISHED: 1998, SOURCE: Proceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology in 1998 5TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY PROCEEDINGS
AUTHORS: Yin, GH; Ahmed, K; Shamlou, D; Grilo, J; Law, S; Wong, C; Paulino, N;
PUBLISHED: 1998, SOURCE: Proceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology in 1998 5TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY PROCEEDINGS
105
TITLE: PROGRAMMABLE CMOS SWITCHED-CAPACITOR BIQUAD USING QUASI-PASSIVE ALGORITHMIC DACS
AUTHORS: PAULINO, N; FRANCA, JE; MARTINS, FP;
PUBLISHED: 1995, SOURCE: IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOLUME: 30, ISSUE: 6
AUTHORS: PAULINO, N; FRANCA, JE; MARTINS, FP;
PUBLISHED: 1995, SOURCE: IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOLUME: 30, ISSUE: 6
INDEXED IN: WOS
WOS IN MY: ORCID
ORCID106
TITLE: Programmable CMOS Switched-Capacitor Biquad Using Quasi-Passive Algorithmic DAC's
AUTHORS: Paulino, N; J.E Franca; F.P Martins;
PUBLISHED: 1995, SOURCE: IEEE Journal of Solid-State Circuits, VOLUME: 30, ISSUE: 6
AUTHORS: Paulino, N; J.E Franca; F.P Martins;
PUBLISHED: 1995, SOURCE: IEEE Journal of Solid-State Circuits, VOLUME: 30, ISSUE: 6
107
TITLE: CHARGE PROGRAMMING TECHNIQUES FOR SC BIQUADS
AUTHORS: MARTINS, FP; PAULINO, NF; FRANCA, JE;
PUBLISHED: 1993, SOURCE: 1993 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS : PROCEEDINGS, VOLS 1-4 ( ISCAS 93 )
AUTHORS: MARTINS, FP; PAULINO, NF; FRANCA, JE;
PUBLISHED: 1993, SOURCE: 1993 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS : PROCEEDINGS, VOLS 1-4 ( ISCAS 93 )
INDEXED IN: WOS
WOS IN MY: ORCID
ORCID