31
TITLE: Programmable logic devices: a test approach for the Input / Output blocks and Pad-to-Pin interconnections
AUTHORS: Manuel G Gericota; Gustavo R Alves; Miguel L Silva; José M Ferreira;
PUBLISHED: 2003
INDEXED IN: Handle
32
TITLE: Concurrent replication of active logic blocks: a core solution for online testing and logic space defragmentation in reconfigurable systems
AUTHORS: Manuel G Gericota; Gustavo R Alves; Miguel L Silva; J. M. Martins Ferreira;
PUBLISHED: 2003
INDEXED IN: Handle
35
TITLE: Dynamic Replication: The Core of a Truly Non-Intrusive SRAM-based FPGA Structural Concurrent Test Methodology
AUTHORS: Manuel G Gericota; Gustavo R. Alves ;
PUBLISHED: 2002, SOURCE: 3rd Latin American Test Workshop, LATW 2002, Montevideo, Uruguay, February 10-13, 2002.
INDEXED IN: DBLP Handle
36
TITLE: AR2T: Implementing a Truly SRAM-based FPGA On-Line Concurrent Testing
AUTHORS: Manuel G Gericota; Gustavo R Alves; Miguel L Silva; Ferreira, J. M. Martins;
PUBLISHED: 2002, SOURCE: 7th European Test Workshop (ETW’02)
INDEXED IN: Handle
37
TITLE: On-line Testing of FPGA Logic Blocks Using Active Replication
AUTHORS: Manuel G Gericota; Gustavo R Alves; Miguel L Silva; José M Ferreira;
PUBLISHED: 2002, SOURCE: Norwegian Computer Science Conference (NIK’02)
INDEXED IN: Handle
38
TITLE: AR2T : implementing a truly SRAM-based FPGA on-line concurrent testing
AUTHORS: Manuel Gericota; Gustavo Alves; Miguel L M da Silva; José M Martins Ferreira;
PUBLISHED: 2002
INDEXED IN: Handle
39
TITLE: On-line testing of FPGA logic blocks using active replication
AUTHORS: Manuel Gericota; Gustavo R Alves; Miguel L Silva; José M M Ferreira;
PUBLISHED: 2002
INDEXED IN: Handle
40
TITLE: Dynamically Rotate And Free for Test: The Path for FPGA Concurrent Test
AUTHORS: Manuel G Gericota; Gustavo R. Alves ; José M Ferreira;
PUBLISHED: 2001, SOURCE: 2nd Latin American Test Workshop, LATW 2001, Cancun, Mexico, February 11-14, 2001.
INDEXED IN: DBLP Handle
Page 4 of 6. Total results: 54.