11
TITLE: VHDL Generation of Optimized FIR Filters
AUTHORS: Fabio Fabian Daitx; Vagner S Rosa; Eduardo Costa; Paulo Flores ; Sergio Bampi;
PUBLISHED: 2008, SOURCE: 2nd International Conference on Signals, Circuits and Systems in SCS: 2008 2ND INTERNATIONAL CONFERENCE ON SIGNALS, CIRCUITS AND SYSTEMS
INDEXED IN: Scopus WOS CrossRef
12
TITLE: Efficient Dedicated Multiplication Blocks for 2's Complement Radix-16 and Radix-256 Array Multipliers
AUTHORS: Leandro Zafalon Pieper; Eduardo A C da Costa; Sergio J M de Almeida; Sergio Bampi; Jose C Monteiro;
PUBLISHED: 2008, SOURCE: 2nd International Conference on Signals, Circuits and Systems in SCS: 2008 2ND INTERNATIONAL CONFERENCE ON SIGNALS, CIRCUITS AND SYSTEMS
INDEXED IN: WOS
13
TITLE: A comparison of layout implementations of pipelined and non-pipelined signed radix-4 array multiplier and modified booth multiplier architectures
AUTHORS: Leonardo L de Oliveira; Cristiano Santos; Daniel Ferrao; Eduardo Costa; Jose Monteiro; Joao Baptista Martins; Sergio Bampi; Ricardo Reis;
PUBLISHED: 2007, SOURCE: 13th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005) in VLSI-SOC: FROM SYSTEMS TO SILICON, VOLUME: 240
INDEXED IN: WOS
14
TITLE: Gray encoded arithmetic operators applied to FFT and FIR dedicated datapaths
AUTHORS: Eduardo A C da Costa; Jose C Monteiro; Sergio Bampi;
PUBLISHED: 2006, SOURCE: 12th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003) in VLSI-SOC: FROM SYSTEMS TO CHIPS, VOLUME: 200
INDEXED IN: WOS
15
TITLE: Design of a radix-2m Hybrid array multiplier using carry save adder
AUTHORS: Fonseca, M; Bampi, S; Da Costa, E; Monteiro, J ;
PUBLISHED: 2005, SOURCE: SBCCI 2005 - 18th Symposium on Integrated Circuits and Systems Design in SBCCI 2005 - 18th Symposium on Integrated Circuits and Systems Design
INDEXED IN: Scopus CrossRef
16
TITLE: A new pipelined array architecture for signed multiplication
AUTHORS: Costa, E; Bampi, S; Monteiro, J;
PUBLISHED: 2003, SOURCE: 16th Symposium on Integrated Circuits and Systems Design in 16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2003, PROCEEDINGS
INDEXED IN: Scopus WOS CrossRef
17
TITLE: Low power architectures for FFT and FIR dedicated datapaths
AUTHORS: Costa, E; Bampi, S; Monteiro, J ;
PUBLISHED: 2003, SOURCE: 46th IEEE International Midwest Symposium on Circuits and Systems in PROCEEDINGS OF THE 46TH IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS & SYSTEMS, VOLS 1-3
INDEXED IN: WOS
18
TITLE: A new architecture for signed Radix-2(m) pure array multipliers  Full Text
AUTHORS: Costa, E; Bampi, S; Monteiro, J ;
PUBLISHED: 2002, SOURCE: 20th IEEE International Conference on Computer Design in ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS
INDEXED IN: Scopus WOS CrossRef
19
TITLE: A new architecture for 2's complement Gray encoded array multiplier
AUTHORS: Costa, E; Bampi, S; Monteiro, J ;
PUBLISHED: 2002, SOURCE: 15th Symposium on Integrated Circuits and Systems Design in 15TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS
INDEXED IN: WOS
20
TITLE: Power efficient arithmetic operand encoding
AUTHORS: Costa, E; Bampi, S; Monteiro, J ;
PUBLISHED: 2001, SOURCE: 14th Symposium on Integrated Circuits and Systems Design in 14TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS
INDEXED IN: WOS
Page 2 of 3. Total results: 21.