Aleksandar Ilic


AuthID: R-001-NJ1

Publications Awaiting Confirmation

61
TITLE: Beyond the Roofline: Cache-Aware Power and Energy-Efficiency Modeling for Multi-Cores
AUTHORS: Aleksandar Ilic; Frederico Pratas; Leonel Sousa;
PUBLISHED: 2017, SOURCE: IEEE TRANSACTIONS ON COMPUTERS, VOLUME: 66, ISSUE: 1
INDEXED IN: WOS DBLP
IN MY: DBLP
62
TITLE: GPU Parallelization of HEVC In-Loop Filters
AUTHORS: Biao Wang; Diego F de Souza; Mauricio Alvarez Mesa; Chi Ching Chi; Ben H H Juurlink; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLISHED: 2017, SOURCE: International Journal of Parallel Programming, VOLUME: 45, ISSUE: 6
INDEXED IN: Scopus DBLP
IN MY: DBLP
63
TITLE: GHEVC: An Efficient HEVC Decoder for Graphics Processing Units  Full Text
AUTHORS: Diego F de Souza; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLISHED: 2017, SOURCE: IEEE TRANSACTIONS ON MULTIMEDIA, VOLUME: 19, ISSUE: 3
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: DBLP
64
TITLE: Energy-aware mechanism for stencil-based MPDATA algorithm with constraints  Full Text
AUTHORS: Krzysztof Rojek; Aleksandar Ilic; Roman Wyrzykowski; Leonel Sousa;
PUBLISHED: 2017, SOURCE: CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, VOLUME: 29, ISSUE: 8
INDEXED IN: WOS DBLP
IN MY: DBLP
65
TITLE: Cache-aware Roofline Model in Intel® Advisor
AUTHORS: Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2017, SOURCE: ERCIM News, VOLUME: 2017, ISSUE: 110
INDEXED IN: DBLP
IN MY: DBLP
66
TITLE: Performance Analysis with Cache-Aware Roofline Model in Intel Advisor
AUTHORS: Diogo Marques; Helder Duarte; Aleksandar Ilic; Leonel Sousa; Roman Belenov; Philippe Thierry; Zakhar A Matveev;
PUBLISHED: 2017, SOURCE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
INDEXED IN: DBLP
IN MY: DBLP
67
TITLE: Analyzing Performance of Multi-cores and Applications with Cache-aware Roofline Model
AUTHORS: Diogo Marques; Helder Duarte; Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2017, SOURCE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
INDEXED IN: DBLP
IN MY: DBLP
68
TITLE: GPU Parallelization of HEVC In-Loop Filters
AUTHORS: Biao Wang; Diego F de Souza; Mauricio Alvarez Mesa; Chi Ching Chi; Ben Juurlink; Aleksandar Ilic; Nuno Roma ; Leonel Sousa;
PUBLISHED: 2017, SOURCE: INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, VOLUME: 45, ISSUE: 6
INDEXED IN: WOS CrossRef
69
TITLE: Modeling Large Compute Nodes with Heterogeneous Memories with Cache-Aware Roofline Model
AUTHORS: Nicolas Denoyelle; Brice Goglin; Aleksandar Ilic; Emmanuel Jeannot; Leonel Sousa;
PUBLISHED: 2017, SOURCE: High Performance Computing Systems. Performance Modeling, Benchmarking, and Simulation - 8th International Workshop, PMBS 2017, Denver, CO, USA, November 13, 2017, Proceedings, VOLUME: 10724
INDEXED IN: DBLP
IN MY: DBLP
70
TITLE: Cache-aware Roofline Model in Intel (R) Advisor
AUTHORS: Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2017, SOURCE: ERCIM NEWS, ISSUE: 110
INDEXED IN: WOS
Page 7 of 15. Total results: 142.

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