Horácio Cláudio de Campos Neto
AuthID: R-000-5ZS
51
TITLE: A reconfigurable computing architecture using magnetic tunneling junction memories
AUTHORS: Silva, V; Fernandes, J ; Vestias, M ; Neto, H;
PUBLISHED: 2013, SOURCE: 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 in 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
AUTHORS: Silva, V; Fernandes, J ; Vestias, M ; Neto, H;
PUBLISHED: 2013, SOURCE: 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 in 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
52
TITLE: Decimal division using the newton-raphson method and radix-1000 arithmetic
AUTHORS: Vestias, MP; Neto, HC;
PUBLISHED: 2013, SOURCE: Embedded Systems Design with FPGAs
AUTHORS: Vestias, MP; Neto, HC;
PUBLISHED: 2013, SOURCE: Embedded Systems Design with FPGAs
INDEXED IN: 
Scopus
Scopus IN MY: 
ORCID
ORCID53
TITLE: Very low resource table-based FPGA evaluation of elementary functions
AUTHORS: Horacio C Neto; Mario P Vestias ;
PUBLISHED: 2013, SOURCE: International Conference on Reconfigurable Computing and FPGAs (ReConFig) in 2013 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG)
AUTHORS: Horacio C Neto; Mario P Vestias ;
PUBLISHED: 2013, SOURCE: International Conference on Reconfigurable Computing and FPGAs (ReConFig) in 2013 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG)
INDEXED IN: 
WOS
WOS54
TITLE: ANALYSIS OF MATRIX MULTIPLICATION ON HIGH DENSITY VIRTEX-7 FPGA
AUTHORS: Wilson Jose; Ana Rita Silva; Horacio Neto; Mario Vestias ;
PUBLISHED: 2013, SOURCE: 23rd International Conference on Field Programmable Logic and Applications (FPL) in 2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS
AUTHORS: Wilson Jose; Ana Rita Silva; Horacio Neto; Mario Vestias ;
PUBLISHED: 2013, SOURCE: 23rd International Conference on Field Programmable Logic and Applications (FPL) in 2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS
INDEXED IN: WOS
WOS55
TITLE: A RECONFIGURABLE COMPUTING ARCHITECTURE USING MAGNETIC TUNNELING JUNCTION MEMORIES
AUTHORS: Victor Silva; Jorge Fernandes; Mario Vestias ; Horacio Neto;
PUBLISHED: 2013, SOURCE: 23rd International Conference on Field Programmable Logic and Applications (FPL) in 2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS
AUTHORS: Victor Silva; Jorge Fernandes; Mario Vestias ; Horacio Neto;
PUBLISHED: 2013, SOURCE: 23rd International Conference on Field Programmable Logic and Applications (FPL) in 2013 23RD INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2013) PROCEEDINGS
INDEXED IN: WOS
WOS56
TITLE: Decimal Division Using the Newton–Raphson Method and Radix-1000 Arithmetic
AUTHORS: Mário P Véstias; Horácio C Neto;
PUBLISHED: 2012, SOURCE: Embedded Systems Design with FPGAs
AUTHORS: Mário P Véstias; Horácio C Neto;
PUBLISHED: 2012, SOURCE: Embedded Systems Design with FPGAs
57
TITLE: Non-Volane Memory Circuits for FIMS and TAS Writing Techniques on Magnetic Tunnelling Junctions
AUTHORS: Victor Silva; Mario P Vestias ; Horacio C Neto; Jorge R Fernandes;
PUBLISHED: 2012, SOURCE: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
AUTHORS: Victor Silva; Mario P Vestias ; Horacio C Neto; Jorge R Fernandes;
PUBLISHED: 2012, SOURCE: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) in 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
INDEXED IN: WOS
WOS58
TITLE: Dynamically reconfigurable networks-on-chip using runtime adaptive routers
AUTHORS: Vestias, MP; Neto, HC;
PUBLISHED: 2010, SOURCE: Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication
AUTHORS: Vestias, MP; Neto, HC;
PUBLISHED: 2010, SOURCE: Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication
INDEXED IN: Scopus
Scopus IN MY: ORCID
ORCID59
TITLE: Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers
AUTHORS: Mário P Véstias; Horácio C Neto;
PUBLISHED: 2010, SOURCE: Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication
AUTHORS: Mário P Véstias; Horácio C Neto;
PUBLISHED: 2010, SOURCE: Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication
60
TITLE: Data-driven regular reconfigurable arrays: Design space exploration and mapping Full Text
AUTHORS: Ferreira, R; Cardoso, JMP ; Toledo, A; Neto, HC;
PUBLISHED: 2005, SOURCE: 5th International Workshop on Embedded Computer Systems - Architectures, Modeling,, and Simulation in EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, VOLUME: 3553
AUTHORS: Ferreira, R; Cardoso, JMP ; Toledo, A; Neto, HC;
PUBLISHED: 2005, SOURCE: 5th International Workshop on Embedded Computer Systems - Architectures, Modeling,, and Simulation in EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, VOLUME: 3553
