Horácio Cláudio de Campos Neto
AuthID: R-000-5ZS
61
TITLE: Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers
AUTHORS: Mário P Véstias; Horácio C Neto;
PUBLISHED: 2010, SOURCE: Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication
AUTHORS: Mário P Véstias; Horácio C Neto;
PUBLISHED: 2010, SOURCE: Dynamic Reconfigurable Network-on-Chip Design - Innovations for Computational Processing and Communication
62
TITLE: Data-driven regular reconfigurable arrays: Design space exploration and mapping
AUTHORS: Ferreira, R; Cardoso, JMP ; Toledo, A; Neto, HC;
PUBLISHED: 2005, SOURCE: 5th International Workshop on Embedded Computer Systems - Architectures, Modeling,, and Simulation in EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, VOLUME: 3553
AUTHORS: Ferreira, R; Cardoso, JMP ; Toledo, A; Neto, HC;
PUBLISHED: 2005, SOURCE: 5th International Workshop on Embedded Computer Systems - Architectures, Modeling,, and Simulation in EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, VOLUME: 3553
63
TITLE: An efficient, low resource, architecture for backpropagation neural networks
AUTHORS: Domingos, PO; Neto, HC;
PUBLISHED: 2005, SOURCE: International Workshop on Applied Reconfigurable Computing 2005, ARC 2005 in ARC 2005 - International Workshop on Applied Reconfigurable Computing 2005
AUTHORS: Domingos, PO; Neto, HC;
PUBLISHED: 2005, SOURCE: International Workshop on Applied Reconfigurable Computing 2005, ARC 2005 in ARC 2005 - International Workshop on Applied Reconfigurable Computing 2005
INDEXED IN: 
Scopus
Scopus IN MY: 
ORCID
ORCID64
TITLE: An environment for exploring data-driven architectures
AUTHORS: Ferreira, R; Cardoso, JMP ; Neto, HC;
PUBLISHED: 2004, SOURCE: 14th International Conference on Field-Programmable Logic and Applications in FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLUME: 3203
AUTHORS: Ferreira, R; Cardoso, JMP ; Neto, HC;
PUBLISHED: 2004, SOURCE: 14th International Conference on Field-Programmable Logic and Applications in FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLUME: 3203
65
TITLE: A modular reconfigurable architecture for efficient fault simulation in digital circuits
AUTHORS: Augusto, JS ; Almeida, CB; Neto, HCC;
PUBLISHED: 2003, SOURCE: 13th International Conference on Field-Programmable Logic and Applications (FPL 2003) in FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLUME: 2778
AUTHORS: Augusto, JS ; Almeida, CB; Neto, HCC;
PUBLISHED: 2003, SOURCE: 13th International Conference on Field-Programmable Logic and Applications (FPL 2003) in FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLUME: 2778
66
TITLE: DALI: A methodology for the co-design of dataflow applications on hardware/software architectures
AUTHORS: Vestias, MP ; Neto, HC;
PUBLISHED: 2003, SOURCE: 16th Symposium on Integrated Circuits and Systems Design in 16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2003, PROCEEDINGS
AUTHORS: Vestias, MP ; Neto, HC;
PUBLISHED: 2003, SOURCE: 16th Symposium on Integrated Circuits and Systems Design in 16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2003, PROCEEDINGS
INDEXED IN: 
WOS
WOS67
TITLE: DALI: A methodology for the co-design of dataflow applications on hardware/software architectures [video encoder DSP example]
AUTHORS: Véstias, MP; Neto, HC;
PUBLISHED: 2003, SOURCE: 16th Symposium on Integrated Circuits and Systems Design, SBCCI 2003 in Proceedings - 16th Symposium on Integrated Circuits and Systems Design, SBCCI 2003
AUTHORS: Véstias, MP; Neto, HC;
PUBLISHED: 2003, SOURCE: 16th Symposium on Integrated Circuits and Systems Design, SBCCI 2003 in Proceedings - 16th Symposium on Integrated Circuits and Systems Design, SBCCI 2003
INDEXED IN: Scopus
Scopus IN MY: ORCID
ORCID68
TITLE: System-level co-synthesis of dataflow dominated applications on reconfigurable hardware/software architectures Full Text
AUTHORS: Vestias, MP ; Neto, HC;
PUBLISHED: 2002, SOURCE: 13th IEEE International Workshop on Rapid System Prototyping in 13TH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS, VOLUME: 2002-January
AUTHORS: Vestias, MP ; Neto, HC;
PUBLISHED: 2002, SOURCE: 13th IEEE International Workshop on Rapid System Prototyping in 13TH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS, VOLUME: 2002-January
69
TITLE: Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines
AUTHORS: João M P Cardoso ; Horácio C Neto;
PUBLISHED: 2001, SOURCE: FPL, VOLUME: 2147
AUTHORS: João M P Cardoso ; Horácio C Neto;
PUBLISHED: 2001, SOURCE: FPL, VOLUME: 2147
70
TITLE: Fast hardware compilation of behaviors into an FPGA-based dynamic reconfigurable computing system
AUTHORS: Joéo M P Cardoso ; Horácio C Neto;
PUBLISHED: 1999, SOURCE: Proceedings - 12th Symposium on Integrated Circuits and Systems Design, SBCCI 1999
AUTHORS: Joéo M P Cardoso ; Horácio C Neto;
PUBLISHED: 1999, SOURCE: Proceedings - 12th Symposium on Integrated Circuits and Systems Design, SBCCI 1999
