José Carlos Alves Pereira Monteiro
AuthID: R-000-85F
41
TITLE: Efficient Dedicated Multiplication Blocks for 2's Complement Radix-16 and Radix-256 Array Multipliers
AUTHORS: Leandro Zafalon Pieper; Eduardo A C da Costa; Sergio J M de Almeida; Sergio Bampi; Jose C Monteiro;
PUBLISHED: 2008, SOURCE: 2nd International Conference on Signals, Circuits and Systems in SCS: 2008 2ND INTERNATIONAL CONFERENCE ON SIGNALS, CIRCUITS AND SYSTEMS
AUTHORS: Leandro Zafalon Pieper; Eduardo A C da Costa; Sergio J M de Almeida; Sergio Bampi; Jose C Monteiro;
PUBLISHED: 2008, SOURCE: 2nd International Conference on Signals, Circuits and Systems in SCS: 2008 2ND INTERNATIONAL CONFERENCE ON SIGNALS, CIRCUITS AND SYSTEMS
INDEXED IN: 
WOS
WOS42
TITLE: A comparison of layout implementations of pipelined and non-pipelined signed radix-4 array multiplier and modified booth multiplier architectures
AUTHORS: Leonardo L de Oliveira; Cristiano Santos; Daniel Ferrao; Eduardo Costa; Jose Monteiro; Joao Baptista Martins; Sergio Bampi; Ricardo Reis;
PUBLISHED: 2007, SOURCE: 13th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005) in VLSI-SOC: FROM SYSTEMS TO SILICON, VOLUME: 240
AUTHORS: Leonardo L de Oliveira; Cristiano Santos; Daniel Ferrao; Eduardo Costa; Jose Monteiro; Joao Baptista Martins; Sergio Bampi; Ricardo Reis;
PUBLISHED: 2007, SOURCE: 13th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005) in VLSI-SOC: FROM SYSTEMS TO SILICON, VOLUME: 240
INDEXED IN: WOS
WOS43
TITLE: Gray encoded arithmetic operators applied to FFT and FIR dedicated datapaths
AUTHORS: Eduardo A C da Costa; Jose C Monteiro; Sergio Bampi;
PUBLISHED: 2006, SOURCE: 12th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003) in VLSI-SOC: FROM SYSTEMS TO CHIPS, VOLUME: 200
AUTHORS: Eduardo A C da Costa; Jose C Monteiro; Sergio Bampi;
PUBLISHED: 2006, SOURCE: 12th International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003) in VLSI-SOC: FROM SYSTEMS TO CHIPS, VOLUME: 200
INDEXED IN: WOS
WOS44
TITLE: Precomputation-based Sequential Logic Optimization For Low Power
AUTHORS: Alidina, M; Monteiro, J; Devadas, S; Ghosh, A; Papefthymiou, M;
PUBLISHED: 2005, SOURCE: IEEE/ACM International Conference on Computer-Aided Design
AUTHORS: Alidina, M; Monteiro, J; Devadas, S; Ghosh, A; Papefthymiou, M;
PUBLISHED: 2005, SOURCE: IEEE/ACM International Conference on Computer-Aided Design
45
TITLE: Low Power Architectures for FFT and FIR Dedicated Datapaths
AUTHORS: Costa, E; Bampi, S; Monteiro, J;
PUBLISHED: 2003, SOURCE: 46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003 in Midwest Symposium on Circuits and Systems, VOLUME: 3
AUTHORS: Costa, E; Bampi, S; Monteiro, J;
PUBLISHED: 2003, SOURCE: 46th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2003 in Midwest Symposium on Circuits and Systems, VOLUME: 3
46
TITLE: Optimization of combinational and sequential logic circuits for low power using precomputation
AUTHORS: Monteiro, J; Rinderknecht, J; Devadas, S; Ghosh, A;
PUBLISHED: 2002, SOURCE: Proceedings Sixteenth Conference on Advanced Research in VLSI
AUTHORS: Monteiro, J; Rinderknecht, J; Devadas, S; Ghosh, A;
PUBLISHED: 2002, SOURCE: Proceedings Sixteenth Conference on Advanced Research in VLSI
47
TITLE: Retiming sequential circuits for low power
AUTHORS: Monteiro, J; Devadas, S; Ghosh, A;
PUBLISHED: 2002, SOURCE: Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)
AUTHORS: Monteiro, J; Devadas, S; Ghosh, A;
PUBLISHED: 2002, SOURCE: Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)
48
TITLE: Probabilistic bottom-up RTL power estimation
AUTHORS: Ferreira, R; A.-M Trullemans; Costa, J; Monteiro, J;
PUBLISHED: 2002, SOURCE: Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)
AUTHORS: Ferreira, R; A.-M Trullemans; Costa, J; Monteiro, J;
PUBLISHED: 2002, SOURCE: Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)
49
TITLE: Power efficient arithmetic operand encoding [CMOS circuits]
AUTHORS: Costa, E; Bampi, S; Monteiro, J;
PUBLISHED: 2001, SOURCE: 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001 in Proceedings - 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001
AUTHORS: Costa, E; Bampi, S; Monteiro, J;
PUBLISHED: 2001, SOURCE: 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001 in Proceedings - 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001
50
TITLE: Power optimized Viterbi decoder implementation through architectural transforms
AUTHORS: Portela, J; Monteiro, J;
PUBLISHED: 2001, SOURCE: 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001 in Proceedings - 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001
AUTHORS: Portela, J; Monteiro, J;
PUBLISHED: 2001, SOURCE: 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001 in Proceedings - 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001
