José Carlos Alves Pereira Monteiro
AuthID: R-000-85F
51
TITLE: A probabilistic approach for RT-level power modeling
AUTHORS: Costa, J; Monteiro, J; Silveira, L. Miguel ; Devadas, S;
PUBLISHED: 1999, SOURCE: 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999 in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, VOLUME: 2
AUTHORS: Costa, J; Monteiro, J; Silveira, L. Miguel ; Devadas, S;
PUBLISHED: 1999, SOURCE: 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999 in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, VOLUME: 2
52
TITLE: Computer-Aided Design Techniques for Low Power Sequential Logic Circuits
AUTHORS: José Monteiro; Srinivas Devadas;
PUBLISHED: 1997
AUTHORS: José Monteiro; Srinivas Devadas;
PUBLISHED: 1997
53
TITLE: Power estimation methods for sequential logic circuits Full Text
AUTHORS: Chi-Ying Tsui, ; Monteiro, J; Massoud Pedram, ; Srinivas Devadas, ; A.M Despain; Lin, B;
PUBLISHED: 1995, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems - IEEE Trans. VLSI Syst., VOLUME: 3, ISSUE: 3
AUTHORS: Chi-Ying Tsui, ; Monteiro, J; Massoud Pedram, ; Srinivas Devadas, ; A.M Despain; Lin, B;
PUBLISHED: 1995, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems - IEEE Trans. VLSI Syst., VOLUME: 3, ISSUE: 3
