111
TITLE: Highly parallel HEVC decoding for heterogeneous systems with CPU and GPU
AUTHORS: Biao Wang; Diego F de Souza; Mauricio Alvarez Mesa; Chi Ching Chi; Ben H H Juurlink; Aleksandar Ilic; Nuno Roma; Leonel Sousa;
PUBLISHED: 2018, SOURCE: Sig. Proc.: Image Comm., VOLUME: 62
INDEXED IN: DBLP
IN MY: DBLP
112
TITLE: Beamformed Fingerprint Learning for Accurate Millimeter Wave Positioning PDF
AUTHORS: João Gante; Gabriel Falcão; Leonel Sousa;
PUBLISHED: 2018, SOURCE: CoRR, VOLUME: abs/1804.04112
INDEXED IN: DBLP arXiv
IN MY: DBLP
113
TITLE: Temperature-aware dynamic voltage and frequency scaling enabled MPSoC modeling using Stochastic Activity Networks  Full Text
AUTHORS: Golnaz Taheri; Ahmak Khonsari; Reza Entezari Maleki; Mohammad Baharloo; Leonel Sousa;
PUBLISHED: 2018, SOURCE: MICROPROCESSORS AND MICROSYSTEMS, VOLUME: 60
INDEXED IN: Scopus WOS
114
TITLE: DATA-AIDED FAST BEAMFORMING SELECTION FOR 5G
AUTHORS: Gante, J; Falcao, G ; Sousa, L;
PUBLISHED: 2018, SOURCE: IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) in 2018 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP)
INDEXED IN: WOS DBLP
IN MY: DBLP
115
TITLE: Configurable N-fold Hardware Architecture for Convolutional Neural Networks
AUTHORS: Dario Baptista; Morgado Dias, F; Leonel Sousa;
PUBLISHED: 2018, SOURCE: International Conference on Biomedical Engineering and Applications (ICBEA) in 2018 INTERNATIONAL CONFERENCE ON BIOMEDICAL ENGINEERING AND APPLICATIONS (ICBEA)
INDEXED IN: WOS
116
TITLE: Performability-Based Workflow Scheduling in Grids
AUTHORS: Reza Entezari Maleki; Kishor S Trivedi; Leonel Sousa; Ali Movaghar;
PUBLISHED: 2018, SOURCE: COMPUTER JOURNAL, VOLUME: 61, ISSUE: 10
INDEXED IN: WOS
117
TITLE: Configurable N-fold Hardware Architecture for Convolutional Neural Networks
AUTHORS: Daria Baptista; Fernando Morgado Dias; Leonel Sousa;
PUBLISHED: 2018, SOURCE: 2018 International Conference on Biomedical Engineering and Applications, ICBEA 2018, Funchal, Portugal, July 9-12, 2018
INDEXED IN: DBLP
IN MY: DBLP
118
TITLE: Towards Efficient Modular Adders based on Reversible Circuits
AUTHORS: Amir Sabbagh Molahosseini; Ailin Asadpoor; Azadeh Alsadat Emrani Zarandi; Leonel Sousa;
PUBLISHED: 2018, SOURCE: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy
INDEXED IN: DBLP
IN MY: DBLP
119
TITLE: Analysis of Scheduling Policies in Metaheuristics for Evolutionary Biology
AUTHORS: Sergio Santander Jiménez; Miguel A Vega Rodríguez; Leonel Sousa;
PUBLISHED: 2018, SOURCE: Proceedings of the 6th International Workshop on Parallelism in Bioinformatics, PBio@EuroMPI 2018, Barcelona, Spain, September 23, 2018
INDEXED IN: DBLP
IN MY: DBLP
120
TITLE: 3D-HEVC DMM-1 Parallelism Exploration Targeting Multicore Systems
AUTHORS: Gustavo Sanchez; Luciano Luciano Agostini; Leonel Sousa; César A M Marcon;
PUBLISHED: 2018, SOURCE: 31st Symposium on Integrated Circuits and Systems Design, SBCCI 2018, Bento Gonçalves, RS, Brazil, August 27-31, 2018
INDEXED IN: DBLP
IN MY: DBLP
Page 12 of 16. Total results: 157.