121
TITLE: Performability-Based Workflow Scheduling in Grids
AUTHORS: Reza Entezari Maleki; Kishor S Trivedi; Leonel Sousa; Ali Movaghar;
PUBLISHED: 2018, SOURCE: Comput. J., VOLUME: 61, ISSUE: 10
INDEXED IN: DBLP
IN MY: DBLP
122
TITLE: Guest Editors' Introduction
AUTHORS: Min Chen; Yang Lei; Leonel Sousa; Yao Zhao; Nan Zhu; Yangdi Lu; Wenbo He; Yu Hua; Jike Ge;
PUBLISHED: 2018, SOURCE: Int. J. Semantic Computing, VOLUME: 12, ISSUE: 2
INDEXED IN: DBLP
IN MY: DBLP
123
TITLE: Temperature-aware dynamic voltage and frequency scaling enabled MPSoC modeling using Stochastic Activity Networks
AUTHORS: Golnaz Taheri; Ahmad Khonsari; Reza Entezari Maleki; Mohammad Baharloo; Leonel Sousa;
PUBLISHED: 2018, SOURCE: Microprocessors and Microsystems - Embedded Hardware Design, VOLUME: 60
INDEXED IN: DBLP
IN MY: DBLP
124
TITLE: Multiobjective Frog-Leaping Optimization for the Study of Ancestral Relationships in Protein Data
AUTHORS: Sergio Santander Jiménez; Miguel A Vega Rodríguez; Leonel Sousa;
PUBLISHED: 2018, SOURCE: IEEE Trans. Evolutionary Computation, VOLUME: 22, ISSUE: 6
INDEXED IN: DBLP
IN MY: DBLP
125
TITLE: Phylogenetic Reconstructions Using an Indicator-Based Bat Algorithm for Multicore Processors
AUTHORS: Sergio Santander Jimenez; Miguel A Vega Rodriguez; Leonel Sousa;
PUBLISHED: 2018, SOURCE: IEEE International Conference on Bioinformatics and Biomedicine (BIBM) in PROCEEDINGS 2018 IEEE INTERNATIONAL CONFERENCE ON BIOINFORMATICS AND BIOMEDICINE (BIBM)
INDEXED IN: WOS
126
TITLE: Accelerating CNN computation: quantisation tuning and network resizing
AUTHORS: Alexandre Vieira; Frederico Pratas; Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2018, SOURCE: Proceedings of the 2nd Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, ANDARE@PACT 2018, Limassol, Cyprus, November 4, 2018
INDEXED IN: DBLP
IN MY: DBLP
127
TITLE: Cache-Aware Roofline Model and Medical Image Processing Optimizations in GPUs
AUTHORS: Estefania Serrano; Aleksandar Ilic; Leonel Sousa; Javier García Blas; Jesús Carretero;
PUBLISHED: 2018, SOURCE: High Performance Computing - ISC High Performance 2018 International Workshops, Frankfurt/Main, Germany, June 28, 2018, Revised Selected Papers, VOLUME: 11203
INDEXED IN: DBLP
IN MY: DBLP
128
TITLE: Cache-aware Roofline Model in Intel® Advisor
AUTHORS: Leonel Sousa; Aleksandar Ilic;
PUBLISHED: 2017, SOURCE: ERCIM News, VOLUME: 2017, ISSUE: 110
INDEXED IN: DBLP
IN MY: DBLP
129
TITLE: Efficient reductions in cyclotomic rings - Application to R-LWE based FHE schemes
AUTHORS: Jean Claude Bajard; Julien Eynard; Anwar Hasan; Paulo Martins; Leonel Sousa; Vincent Zucca;
PUBLISHED: 2017, SOURCE: IACR Cryptology ePrint Archive, VOLUME: 2017
INDEXED IN: DBLP
IN MY: DBLP
130
TITLE: A Reduced-Bias Approach With a Lightweight Hard-Multiple Generator to Design a Radix-8 Modulo 2n + 1 Multiplier
AUTHORS: Seyed Mostafa Mirhosseini; Amir Sabbagh Molahosseini; Mehdi Hosseinzadeh; Leonel Sousa; Paulo Martins;
PUBLISHED: 2017, SOURCE: IEEE Trans. on Circuits and Systems, VOLUME: 64, ISSUE: 7
INDEXED IN: DBLP
IN MY: DBLP
Page 13 of 16. Total results: 157.