Nuno Filipe Valentim Roma


AuthID: R-000-DNS

Confirmed Publications: 140



131
TITLE: Automatic synthesis of motion estimation processors based on a new class of hardware architectures
AUTHORS: Roma, N ; Sousa, L ;
PUBLISHED: 2003, SOURCE: IEEE Workshop on Signal Processing, Systems Design and Implementation (SiPS 01) in JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, VOLUME: 34, ISSUE: 3
INDEXED IN: Scopus WOS DBLP CrossRef: 1
IN MY: ORCID
132
TITLE: Customisable core-based architectures for real-time motion estimation on FPGAs
AUTHORS: Roma, N ; Dias, T; Sousa, L ;
PUBLISHED: 2003, SOURCE: 13th International Conference on Field-Programmable Logic and Applications (FPL 2003) in FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLUME: 2778
INDEXED IN: Scopus WOS DBLP CrossRef: 9
IN MY: ORCID
133
TITLE: Fast transcoding architectures for insertion of non-regular shaped objects in the compresse DCT-domain  Full Text
AUTHORS: Roma, N ; Sousa, L ;
PUBLISHED: 2003, SOURCE: SIGNAL PROCESSING-IMAGE COMMUNICATION, VOLUME: 18, ISSUE: 8
INDEXED IN: WOS
134
TITLE: Fast transcoding architectures for insertion of non-regular shaped objects in the compressed DCT-domain
AUTHORS: Nuno Roma ; Leonel Sousa ;
PUBLISHED: 2003, SOURCE: Signal Process. Image Commun., VOLUME: 18, ISSUE: 8
INDEXED IN: Scopus DBLP CrossRef: 2
IN MY: ORCID
135
TITLE: Efficient and configurable full-search block-matching processors  Full Text
AUTHORS: Roma, N ; Sousa, L ;
PUBLISHED: 2002, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOLUME: 12, ISSUE: 12
INDEXED IN: Scopus WOS DBLP CrossRef: 33
IN MY: ORCID
136
TITLE: Insertion of irregular-shaped logos in the compressed DCT domain
AUTHORS: Roma, N ; Sousa, L ;
PUBLISHED: 2002, SOURCE: 14th International Conference on Digital Signal Processing (DSP 2002) in DSP 2002: 14TH INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING PROCEEDINGS, VOLS 1 AND 2, VOLUME: 1
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID
137
138
TITLE: Parameterizable hardware architectures for automatic synthesis of motion estimation processors
AUTHORS: Roma, N ; Sousa, L ;
PUBLISHED: 2001, SOURCE: IEEE Workshop on Signal Processing, Systems Design and Implementation (SiPS 01) in SIPS 2001: IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION
INDEXED IN: Scopus WOS
IN MY: ORCID | CIÊNCIAVITAE
139
TITLE: In the development and evaluation of specialized processors for computing high-order 2-D image moments in real-time
AUTHORS: Roma, N ; Sousa, L ;
PUBLISHED: 2000, SOURCE: 5th IEEE International Workshop on Computer Architectures for Machine Perception (CAMP 2000) in 5TH INTERNATIONAL WORKSHOP ON COMPUTER ARCHITECTURES FOR MACHINE PERCEPTION, PROCEEDINGS
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID
140
TITLE: Low-power array architectures for motion estimation
AUTHORS: Leonel Sousa ; Nuno Roma ;
PUBLISHED: 1999, SOURCE: MMSP
INDEXED IN: Scopus DBLP CrossRef: 17
IN MY: ORCID
Page 14 of 14. Total results: 140.

footer slogan

Useful Links

Get Help

© 2026 CRACS & Inesc TEC - All Rights Reserved Privacy Policy | Terms of Service