Nuno Filipe Valentim Roma


AuthID: R-000-DNS

Confirmed Publications: 144



131
TITLE: Customizable and reduced hardware motion estimation processors  Full Text
AUTHORS: Roma, N ; Dias, T; Sousa, L ;
PUBLISHED: 2005, SOURCE: New Algorithms, Architectures and Applications for Reconfigurable Computing
INDEXED IN: Scopus CrossRef
IN MY: ORCID | CIÊNCIAVITAE
132
TITLE: Efficient motion vector refinement architecture for sub-pixel motion estimation systems  Full Text
AUTHORS: Dias, T; Roma, N ; Sousa, L ;
PUBLISHED: 2005, SOURCE: IEEE Workshop on Signal Processing Systems Design and Implementations (SiPS 05) in 2005 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS - DESIGN AND IMPLEMENTATION (SIPS), VOLUME: 2005
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
133
TITLE: Efficient VLSI architecture for real-time motion estimation in advanced video coding
AUTHORS: Dias, T; Roma, N ; Sousa, L ;
PUBLISHED: 2005, SOURCE: IEEE International SOC Conference in IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | CIÊNCIAVITAE
134
TITLE: Least squares motion estimation algorithm in the compressed DCT domain for H.26x/MPEG-x video sequences
AUTHORS: Roma, N ; Sousa, L ;
PUBLISHED: 2005, SOURCE: IEEE Conference on Advanced Video and Signal Based Surveillance in AVSS 2005: ADVANCED VIDEO AND SIGNAL BASED SURVEILLANCE, PROCEEDINGS, VOLUME: 2005
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | CIÊNCIAVITAE
135
TITLE: Automatic synthesis of motion estimation processors based on a new class of hardware architectures
AUTHORS: Roma, N ; Sousa, L ;
PUBLISHED: 2003, SOURCE: IEEE Workshop on Signal Processing, Systems Design and Implementation (SiPS 01) in JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, VOLUME: 34, ISSUE: 3
INDEXED IN: Scopus WOS DBLP CrossRef: 1
IN MY: ORCID | CIÊNCIAVITAE
136
TITLE: Customisable core-based architectures for real-time motion estimation on FPGAs
AUTHORS: Roma, N ; Dias, T; Sousa, L ;
PUBLISHED: 2003, SOURCE: 13th International Conference on Field-Programmable Logic and Applications (FPL 2003) in FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLUME: 2778
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | CIÊNCIAVITAE
137
TITLE: Fast transcoding architectures for insertion of non-regular shaped objects in the compresse DCT-domain  Full Text
AUTHORS: Roma, N ; Sousa, L ;
PUBLISHED: 2003, SOURCE: SIGNAL PROCESSING-IMAGE COMMUNICATION, VOLUME: 18, ISSUE: 8
INDEXED IN: WOS
138
TITLE: Fast transcoding architectures for insertion of non-regular shaped objects in the compressed DCT-domain  Full Text
AUTHORS: Nuno Roma ; Leonel Sousa ;
PUBLISHED: 2003, SOURCE: Sig. Proc.: Image Comm., VOLUME: 18, ISSUE: 8
INDEXED IN: Scopus DBLP CrossRef
IN MY: ORCID | CIÊNCIAVITAE
139
TITLE: Efficient and configurable full-search block-matching processors  Full Text
AUTHORS: Roma, N ; Sousa, L ;
PUBLISHED: 2002, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOLUME: 12, ISSUE: 12
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | CIÊNCIAVITAE
140
TITLE: Insertion of irregular-shaped logos in the compressed DCT domain
AUTHORS: Roma, N ; Sousa, L ;
PUBLISHED: 2002, SOURCE: 14th International Conference on Digital Signal Processing (DSP 2002) in DSP 2002: 14TH INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING PROCEEDINGS, VOLS 1 AND 2, VOLUME: 1
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | CIÊNCIAVITAE
Page 14 of 15. Total results: 144.

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