11
TITLE: Techniques and Analysis for Mixed-criticality Scheduling with Mode-dependent Server Execution Budgets  Full Text
AUTHORS: Awan, MA; Bletsas, KN; Souto, PF ; Akesson, B; Tovar, E ;
PUBLISHED: 2019, SOURCE: Embedded Systems Week / Int Conf on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) / International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) / Int Conf on Embedded Software (EMSOFT) in ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, VOLUME: 18, ISSUE: 5
INDEXED IN: Scopus WOS DBLP CrossRef Handle
IN MY: ORCID
12
TITLE: Uneven memory regulation for scheduling IMA applications on multi-core platforms  Full Text
AUTHORS: Awan, MA; Souto, PF ; Akesson, B; Bletsas, K; Tovar, E ;
PUBLISHED: 2019, SOURCE: REAL-TIME SYSTEMS, VOLUME: 55, ISSUE: 2
INDEXED IN: Scopus WOS DBLP CrossRef: 6 Handle
IN MY: ORCID
13
TITLE: Mixed-criticality Scheduling with Dynamic Memory Bandwidth Regulation
AUTHORS: Awan, MA; Bletsas, K; Souto, PF ; Akesson, B; Tovar, E ;
PUBLISHED: 2018, SOURCE: 24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA) in 2018 IEEE 24TH INTERNATIONAL CONFERENCE ON EMBEDDED AND REAL-TIME COMPUTING SYSTEMS AND APPLICATIONS (RTCSA)
INDEXED IN: Scopus WOS DBLP CrossRef: 6 Handle
IN MY: ORCID
14
TITLE: Mixed-criticality scheduling with memory bandwidth regulation  Full Text
AUTHORS: Muhammad Ali Awan; Pedro F Souto ; Konstantinos Bletsas; Benny Akesson; Eduardo Tovar ;
PUBLISHED: 2018, SOURCE: DATE, VOLUME: 2018-January
INDEXED IN: Scopus DBLP CrossRef: 3 Handle
IN MY: ORCID
15
TITLE: Mixed-criticality Scheduling with Memory Bandwidth Regulation
AUTHORS: Awan, Muhammad Ali; Souto, Pedro F. ; Bletsas, Konstantinos; Akesson, Benny; Tovar, Eduardo;
PUBLISHED: 2018, SOURCE: Design, Automation and Test in Europe Conference and Exhibition (DATE) in PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)
INDEXED IN: WOS
16
TITLE: Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers
AUTHORS: Muhammad Ali Awan; Pedro F Souto ; Konstantinos Bletsas; Benny Akesson; Eduardo Tovar ;
PUBLISHED: 2018, SOURCE: ECRTS, VOLUME: 106
INDEXED IN: Scopus DBLP Handle
17
TITLE: Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)
AUTHORS: Muhammad Ali Awan; Pedro F Souto ; Konstantinos Bletsas; Benny Akesson; Eduardo Tovar ;
PUBLISHED: 2018, SOURCE: Dagstuhl Artifacts Ser., VOLUME: 4, ISSUE: 2
INDEXED IN: DBLP Handle
18
TITLE: Mixed-Criticality Scheduling with Dynamic Redistribution of Shared Cache
AUTHORS: Muhammad Ali Awan; Konstantinos Bletsas; Pedro F Souto ; Benny Akesson; Eduardo Tovar ;
PUBLISHED: 2017, SOURCE: ECRTS, VOLUME: 76
INDEXED IN: Scopus DBLP Handle
19
TITLE: Semi-partitioned Mixed-Criticality Scheduling
AUTHORS: Muhammad Ali Awan; Konstantinos Bletsas; Pedro F Souto ; Eduardo Tovar ;
PUBLISHED: 2017, SOURCE: ARCS, VOLUME: 10172 LNCS
INDEXED IN: Scopus DBLP CrossRef: 10
IN MY: ORCID
20
TITLE: A review of scalability and topological stability issues in IEEE 802.11s wireless mesh networks deployments  Full Text
AUTHORS: Sampaio, S ; Souto, P ; Vasques, F ;
PUBLISHED: 2016, SOURCE: INTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMS, VOLUME: 29, ISSUE: 4
INDEXED IN: Scopus WOS DBLP CrossRef: 13 Handle
IN MY: ORCID
Page 2 of 4. Total results: 37.