Gustavo Ribeiro da Costa Alves


AuthID: R-000-K2T

Confirmed Publications: 251



241
TITLE: A system verification strategy based on the BST infrastructure
AUTHORS: Gustavo R. Alves ; Ferreira, JMM;
PUBLISHED: 1999, SOURCE: 1999 IEEE International Symposium on Circuits and Systems (ISCAS 99) in ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, VOLUME: 1
INDEXED IN: WOS DBLP CrossRef
IN MY: ORCID
242
TITLE: Board-level prototype validation: A built-in controller and extended BST architecture
AUTHORS: Gustavo R. Alves ; Amaral, T; Ferreira, JMM;
PUBLISHED: 1999, SOURCE: 1999 IEEE International Symposium on Circuits and Systems (ISCAS 99) in ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI
INDEXED IN: WOS
IN MY: ORCID | CIÊNCIAVITAE
243
TITLE: Board-level prototype validation: a built-in controller and extended BST architecture
AUTHORS: Gustavo R. Alves ; Telmo Amaral; Martins Ferreira Jose, M;
PUBLISHED: 1999, SOURCE: Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 in Proceedings - IEEE International Symposium on Circuits and Systems, VOLUME: 1
INDEXED IN: Scopus
IN MY: ORCID
244
TITLE: Board-level prototype validation: a built-in controller and extended BST architecture
AUTHORS: Gustavo R. Alves ; Tito G B Amaral; José Manuel Martins Ferreira;
PUBLISHED: 1999, SOURCE: ISCAS (1), VOLUME: 1
INDEXED IN: DBLP CrossRef: 2
IN MY: ORCID
245
TITLE: From design-for-test to design-for-debug-and-test: Analysis of requirements and limitations for 1149.1  Full Text
AUTHORS: Gustavo R. Alves ; Ferreira, JMM;
PUBLISHED: 1999, SOURCE: 17th IEEE Very Large Scale Intergration Test Symposium in 17TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS
INDEXED IN: Scopus WOS DBLP CrossRef: 5
IN MY: ORCID
246
247
TITLE: System verification strategy based on the BST infrastructure
AUTHORS: Gustavo R. Alves ; Martins Ferreira Jose, M;
PUBLISHED: 1999, SOURCE: Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 in Proceedings - IEEE International Symposium on Circuits and Systems, VOLUME: 1
INDEXED IN: Scopus
IN MY: ORCID | CIÊNCIAVITAE
248
TITLE: Using the BS register for capturing and storing n-bit sequences in real-time
AUTHORS: Gustavo R. Alves ; José Manuel Martins Ferreira;
PUBLISHED: 1999, SOURCE: ETW
INDEXED IN: Scopus DBLP CrossRef
IN MY: ORCID
249
TITLE: An HDL approach to board-level BIST  Full Text
AUTHORS: Gustavo R. Alves ; Manuel G Gericota ; José L Ramalho; José Manuel Martins Ferreira;
PUBLISHED: 1993, SOURCE: EURO-DAC
INDEXED IN: DBLP CrossRef Handle
IN MY: ORCID
250
TITLE: BIST FOR 1149.1-COMPATIBLE BOARDS - A LOW-COST AND MAXIMUM-FLEXIBILITY SOLUTION
AUTHORS: FERREIRA, JMM; GERICOTA, MG ; RAMALHO, JL; Gustavo R. Alves ;
PUBLISHED: 1993, SOURCE: International Test Conference 1993: Designing, Testing, and Diagnostics - Join Them in INTERNATIONAL TEST CONFERENCE 1993 PROCEEDINGS
INDEXED IN: Scopus WOS DBLP CrossRef: 3 Handle
IN MY: ORCID
Page 25 of 26. Total results: 251.

footer slogan

Useful Links

Get Help

© 2026 CRACS & Inesc TEC - All Rights Reserved Privacy Policy | Terms of Service