João Paulo de Castro Canas Ferreira


AuthID: R-000-7A5

Confirmed Publications: 95



71
TITLE: Creation of Partial FPGA Configurations at Run-Time
AUTHORS: Silva, ML; Ferreira, JC ;
PUBLISHED: 2010, SOURCE: 13th Euromicro Conference on Digital System Design on Architectures, Methods and Tools in 13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS
INDEXED IN: Scopus WOS DBLP CrossRef: 4
IN MY: ORCID
72
TITLE: Erlang Inspired Hardware  Full Text
AUTHORS: Paulo Ferreira ; João Canas Ferreira ; José Carlos Alves ;
PUBLISHED: 2010, SOURCE: FPL
INDEXED IN: Scopus DBLP CrossRef: 1
IN MY: ORCID
73
TITLE: FPGA-based real-time disparity computation and object location
AUTHORS: Santos, PM ; Ferreira, JC ;
PUBLISHED: 2010, SOURCE: 28th Norchip Conference, NORCHIP 2010 in 28th Norchip Conference, NORCHIP 2010
INDEXED IN: Scopus CrossRef: 3
IN MY: ORCID | ResearcherID
74
TITLE: FPGA-based rectification of stereo images
AUTHORS: João G P Rodrigues; João Canas Ferreira ;
PUBLISHED: 2010, SOURCE: DASIP
INDEXED IN: Scopus DBLP CrossRef: 7
IN MY: ORCID
75
TITLE: Run-time Generation of Partial Configurations for Arithmetic Expressions  Full Text
AUTHORS: Miguel L Silva; Joao Canas Ferreira ;
PUBLISHED: 2010, SOURCE: 53rd Midwest Symposium on Circuits and Systems (MWSCAS 2010) in 53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | ResearcherID
76
TITLE: Non-Rectangular Reconfigurable Cores for System-on-Chip
AUTHORS: Pedro Alves; Joao Canas Ferreira ;
PUBLISHED: 2009, SOURCE: Conference on VLSI Circuits and Systems IV in VLSI CIRCUITS AND SYSTEMS IV, VOLUME: 7363
INDEXED IN: Scopus WOS CrossRef
IN MY: ORCID | ResearcherID
77
TITLE: GENERATION OF PARTIAL FPGA CONFIGURATIONS AT RUN-TIME
AUTHORS: Silva, ML; Ferreira, JC ;
PUBLISHED: 2008, SOURCE: International Conference on Field Programmable and Logic Applications in 2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2
INDEXED IN: Scopus WOS DBLP CrossRef: 15
IN MY: ORCID
78
TITLE: Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems  Full Text
AUTHORS: Silva, ML; Ferreira, JC ;
PUBLISHED: 2007, SOURCE: 20th International Conference on Design of Ciruits and Integrated Systems in IET COMPUTERS AND DIGITAL TECHNIQUES, VOLUME: 1, ISSUE: 5
INDEXED IN: Scopus WOS DBLP CrossRef: 7
IN MY: ORCID
79
TITLE: Exploiting dynamic reconfiguration of platform FPGAs: implementation issues  Full Text
AUTHORS: Miguel L Silva; João Canas Ferreira ;
PUBLISHED: 2006, SOURCE: IPDPS, VOLUME: 2006
INDEXED IN: Scopus DBLP CrossRef: 3
IN MY: ORCID
80
TITLE: Support for partial run-time reconfiguration of platform FPGAs  Full Text
AUTHORS: Silva, ML; Ferreira, JC ;
PUBLISHED: 2006, SOURCE: JOURNAL OF SYSTEMS ARCHITECTURE, VOLUME: 52, ISSUE: 12
INDEXED IN: Scopus WOS DBLP CrossRef: 21
IN MY: ORCID
Page 8 of 10. Total results: 95.

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