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TITLE: An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios  Full Text
AUTHORS: Mario Lopes Ferreira; Joao Canas Ferreira ;
SOURCE: ELECTRONICS, VOLUME: 8, ISSUE: 1, PUBLISHED: 2019
INDEXED IN: Scopus WOS
2
TITLE: Analysis and Evaluation of anEnergy-Efficient Routing Protocol for WSNsCombining Source Routing and MinimumCost Forwarding
AUTHORS: Fardin Derogarian Miyandoab; João Canas Ferreira ; Vítor Grade G Tavares ; Instituto de Telecomunicações and DEM, Universidade da Beira Interior, Faculdade de Engenharia, Portugal, ; INESC TEC, Faculdade de Engenharia da Universidade do Porto, Portugal, ; INESC TEC, Faculdade de Engenharia da Universidade do Porto, Portugal, ;
SOURCE: Journal of Mobile Multimedia, VOLUME: 14, ISSUE: 4, PUBLISHED: 2019
INDEXED IN: CrossRef
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TITLE: Dynamic Partial Reconfiguration of Customized Single-Row Accelerators  Full Text
AUTHORS: Nuno M C Paulino ; Joao Canas Ferreira ; Joao M P Cardoso ;
SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 27, ISSUE: 1, PUBLISHED: 2019
INDEXED IN: WOS DBLP CrossRef
4
TITLE: A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems
AUTHORS: Mário Lopes Ferreira ; João Canas Ferreira ; Michael Hübner;
SOURCE: 14th International Symposium on Applied Reconfigurable Computing, ARC 2018 in Applied Reconfigurable Computing. Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings, VOLUME: 10824, PUBLISHED: 2018
INDEXED IN: Scopus DBLP CrossRef
IN MY: DBLP
5
TITLE: An FPGA array for cellular genetic algorithms: Application to the minimum energy broadcast problem  Full Text
AUTHORS: Pedro Vieira dos Santos; Jose Carlos Alves ; Joao Canas Ferreira ;
SOURCE: 18th Euromicro Conference on Digital System Design (DSD) in MICROPROCESSORS AND MICROSYSTEMS, VOLUME: 58, PUBLISHED: 2018
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: ORCID | DBLP
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TITLE: Design and Evaluation of a Low Power CGRA Accelerator for Biomedical Signal Processing
AUTHORS: Helder H Avelar ; João Canas Ferreira ;
SOURCE: 21st Euromicro Conference on Digital System Design, DSD 2018 in 21st Euromicro Conference on Digital System Design, DSD 2018, Prague, Czech Republic, August 29-31, 2018, PUBLISHED: 2018
INDEXED IN: Scopus DBLP
IN MY: DBLP
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TITLE: Flexible and Dynamically Reconfigurable FPGA-Based FS-FBMC Baseband Modulator
AUTHORS: Mario Lopes Ferreira; Joao Canas Ferreira ;
SOURCE: IEEE International Symposium on Circuits and Systems (ISCAS) in 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLUME: 2018-May, PUBLISHED: 2018
INDEXED IN: Scopus WOS DBLP CrossRef
IN MY: DBLP
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TITLE: Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices
AUTHORS: Joao Lopes; Diogo Sousa; Joao Canas Ferreira ;
SOURCE: International Conference on Reconfigurable Computing and FPGAs (ReConFig) in 2017 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG), PUBLISHED: 2017
INDEXED IN: WOS DBLP CrossRef
IN MY: ORCID | DBLP
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TITLE: FPGA-based Implementation of a Frequency Spreading FBMC-OQAM Baseband Modulator
AUTHORS: Miguel Carvalho; Mario Lopes Ferreira ; Joao Canas Ferreira ;
SOURCE: 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS) in 2017 24TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), PUBLISHED: 2017
INDEXED IN: WOS DBLP CrossRef
IN MY: ORCID | DBLP
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TITLE: Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces  Full Text
AUTHORS: Nuno M C Paulino ; Joao Canas Ferreira ; Joao M P Cardoso ;
SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 25, ISSUE: 1, PUBLISHED: 2017
INDEXED IN: Scopus WOS DBLP CrossRef: 1
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