Amir Sabbagh Molahosseini


AuthID: R-007-0KR

Publications Awaiting Confirmation

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TITLE: Low-Precision Floating-Point Formats: From General-Purpose to Application-Specific
AUTHORS: Molahosseini, AS; Sousa, L; Emrani Zarandi, AA; Vandierendonck, H;
PUBLISHED: 2022, SOURCE: Approximate Computing
INDEXED IN: Scopus
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TITLE: Efficient Modular Adder Designs Based on Thermometer and One-Hot Coding  Full Text
AUTHORS: Fereshteh Jafarzadehpour; Amir Sabbagh Molahosseini; Azadeh Alsadat Emrani Zarandi; Leonel Sousa;
PUBLISHED: 2019, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 27, ISSUE: 9
INDEXED IN: Scopus WOS
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TITLE: New energy-efficient hybrid wide-operand adder architecture
AUTHORS: Fereshteh Jafarzadehpour; Amir Sabbagh Molahosseini; Azadeh Alsadat Emrani Zarandi; Leonel Sousa;
PUBLISHED: 2019, SOURCE: IET CIRCUITS DEVICES & SYSTEMS, VOLUME: 13, ISSUE: 8
INDEXED IN: Scopus WOS
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TITLE: New energy-efficient hybrid wide-operand adder architecture
AUTHORS: Fereshteh Jafarzadehpour; Amir Sabbagh Molahosseini; Azadeh Alsadat Emrani Zarandi; Leonel Sousa;
PUBLISHED: 2019, SOURCE: IET Circuits, Devices & Systems, VOLUME: 13, ISSUE: 8
INDEXED IN: DBLP
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TITLE: Efficient Modular Adder Designs Based on Thermometer and One-Hot Coding
AUTHORS: Fereshteh Jafarzadehpour; Amir Sabbagh Molahosseini; Azadeh Alsadat Emrani Zarandi; Leonel Sousa;
PUBLISHED: 2019, SOURCE: IEEE Trans. Very Large Scale Integr. Syst., VOLUME: 27, ISSUE: 9
INDEXED IN: DBLP
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TITLE: Towards Efficient Modular Adders based on Reversible Circuits
AUTHORS: Amir Sabbagh Molahosseini; Ailin Asadpoor; Azadeh Alsadat Emrani Zarandi; Leonel Sousa;
PUBLISHED: 2018, SOURCE: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy
INDEXED IN: DBLP
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TITLE: An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form {2(k), 2(P)-1}  Full Text
AUTHORS: Azadeh Alsadat Emrani Zarandi; Amir Sabbagh Molahosseini; Leonel Sousa; Mehdi Hosseinzadeh;
PUBLISHED: 2017, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 25, ISSUE: 1
INDEXED IN: WOS DBLP
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TITLE: A Reduced-Bias Approach With a Lightweight Hard-Multiple Generator to Design a Radix-8 Modulo 2n + 1 Multiplier
AUTHORS: Seyed Mostafa Mirhosseini; Amir Sabbagh Molahosseini; Mehdi Hosseinzadeh; Leonel Sousa; Paulo Martins;
PUBLISHED: 2017, SOURCE: IEEE Trans. on Circuits and Systems, VOLUME: 64, ISSUE: 7
INDEXED IN: DBLP
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