12
TITLE: Preface
AUTHORS: Molahosseini, AS; de Seabra, LS; Chang, CH;
PUBLISHED: 2017, SOURCE: Embedded Systems Design with Special Arithmetic and Number Systems
INDEXED IN: Scopus
13
TITLE: Area-delay-power-aware adder placement method for RNS reverse converter design
AUTHORS: Zarandi, AAE; Molahosseini, AS; Sousa, L; Hosseinzadeh, M; Navi, K;
PUBLISHED: 2016, SOURCE: 7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016 in LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference
INDEXED IN: Scopus
14
TITLE: Area-delay-power-aware adder placement method for RNS reverse converter design
AUTHORS: Zarandi, AAE; Molahosseini, AS; Sousa, L; Hosseinzadeh, M; Navi, K;
PUBLISHED: 2016, SOURCE: 7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016 in LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference
INDEXED IN: Scopus
15
TITLE: Area-Delay-Power-Aware Adder Placement Method for RNS Reverse Converter Design
AUTHORS: Azadeh Alsadat Emrani Zarandi; Amir Sabbagh Molahosseini; Leonel Sousa ; Mehdi Hosseinzadeh; Keivan Navi;
PUBLISHED: 2016, SOURCE: 7th IEEE Latin American Symposium on Circuits and Systems (LASCAS) in 2016 IEEE 7TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS)
INDEXED IN: WOS DBLP CrossRef
16
TITLE: Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations  Full Text
AUTHORS: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L ;
PUBLISHED: 2015, SOURCE: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOLUME: 23, ISSUE: 2
INDEXED IN: Scopus WOS DBLP
17
TITLE: Reverse converter design via parallel-prefix adders: Novel components, methodology, and implementations
AUTHORS: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L;
PUBLISHED: 2015, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, ISSUE: 2
INDEXED IN: Scopus
18
TITLE: Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations  Full Text
AUTHORS: Zarandi, AAE; Molahosseini, AS; Hosseinzadeh, M; Sorouri, S; Antao, S; Sousa, L ;
PUBLISHED: 2014, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, VOLUME: 23, ISSUE: 2
INDEXED IN: Scopus CrossRef: 15
Page 2 of 2. Total results: 18.