Johan Vounckx
AuthID: R-00F-DY0
1
TITLE: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings
AUTHORS: Johan Vounckx; Nadine Azémard; Philippe Maurine;
PUBLISHED: 2006, SOURCE: PATMOS, VOLUME: 4148
AUTHORS: Johan Vounckx; Nadine Azémard; Philippe Maurine;
PUBLISHED: 2006, SOURCE: PATMOS, VOLUME: 4148
INDEXED IN: 
DBLP
DBLP2
TITLE: The FTMPS-Project: Design and Implementation of Fault-Tolerance Techniques for Massively Parallel Systems
AUTHORS: Johan Vounckx; Geert Deconinck; Rudy Lauwereins; Viehöver, G; Wagner, R; Henrique Madeira ; João Gabriel Silva ; Frank Balbach; Jörn Altmann; Bernd Bieker; Harald Willeke;
PUBLISHED: 1994, SOURCE: High-Performance Computing and Networking, International Conference and Exhibition, HPCN Europe 1994, Munich, Germany, April 18-20, 1994, Proceedings, Volume II: Networking and Tools, VOLUME: 797
AUTHORS: Johan Vounckx; Geert Deconinck; Rudy Lauwereins; Viehöver, G; Wagner, R; Henrique Madeira ; João Gabriel Silva ; Frank Balbach; Jörn Altmann; Bernd Bieker; Harald Willeke;
PUBLISHED: 1994, SOURCE: High-Performance Computing and Networking, International Conference and Exhibition, HPCN Europe 1994, Munich, Germany, April 18-20, 1994, Proceedings, Volume II: Networking and Tools, VOLUME: 797
INDEXED IN: DBLP 
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