Jeyanandh Paramesh
AuthID: R-00H-H28
1
TITLE: Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs
AUTHORS: Shaolong L Liu; Taimur Rabuske; Jeyanandh Paramesh; Lawrence Pileggi; Jorge Fernandes;
PUBLISHED: 2018, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, VOLUME: 65, ISSUE: 2
AUTHORS: Shaolong L Liu; Taimur Rabuske; Jeyanandh Paramesh; Lawrence Pileggi; Jorge Fernandes;
PUBLISHED: 2018, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, VOLUME: 65, ISSUE: 2
INDEXED IN: 
WOS
WOS2
TITLE: A 125 MS/s 10.4 ENOB 10.1 fJ/cony-step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS
AUTHORS: Shaolong L Liu; Jeyanandh Paramesh; Larry Pileggi; Taimur Rabuske; Jorge Fernandes;
PUBLISHED: 2018, SOURCE: 44th IEEE European Solid State Circuits Conference (ESSCIRC) in ESSCIRC 2018 - IEEE 44TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC)
AUTHORS: Shaolong L Liu; Jeyanandh Paramesh; Larry Pileggi; Taimur Rabuske; Jorge Fernandes;
PUBLISHED: 2018, SOURCE: 44th IEEE European Solid State Circuits Conference (ESSCIRC) in ESSCIRC 2018 - IEEE 44TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC)
INDEXED IN: WOS
WOS3
TITLE: A 125 MS/s 10.4 ENOB 10.1 fJ/Conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS
AUTHORS: Liu, S; Paramesh, J; Pileggi, L; Rabuske, T; Fernandcs, J;
PUBLISHED: 2018, SOURCE: 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018 in ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference
AUTHORS: Liu, S; Paramesh, J; Pileggi, L; Rabuske, T; Fernandcs, J;
PUBLISHED: 2018, SOURCE: 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018 in ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference
INDEXED IN: 
Scopus
Scopus