Nuno Filipe Simões Santos Moraes Neves
AuthID: R-00J-05P
1
TITLE: Trading Performance, Power, and Area on Low-Precision Posit MAC Units for CNN Training
AUTHORS: Crespo, Luis; Tomas, Pedro; Roma, Nuno; Neves, Nuno;
PUBLISHED: 2023, SOURCE: 35th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD) in 2023 IEEE 35TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING, SBAC-PAD
AUTHORS: Crespo, Luis; Tomas, Pedro; Roma, Nuno; Neves, Nuno;
PUBLISHED: 2023, SOURCE: 35th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD) in 2023 IEEE 35TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING, SBAC-PAD
INDEXED IN: 
Scopus 
WOS
Scopus WOS2
TITLE: Compiler-Assisted Data Streaming for Regular Code Structures
AUTHORS: Neves, N; Tomas, P; Roma, N;
PUBLISHED: 2021, SOURCE: IEEE TRANSACTIONS ON COMPUTERS, VOLUME: 70, ISSUE: 3
AUTHORS: Neves, N; Tomas, P; Roma, N;
PUBLISHED: 2021, SOURCE: IEEE TRANSACTIONS ON COMPUTERS, VOLUME: 70, ISSUE: 3
INDEXED IN: Scopus WOS
Scopus WOS3
TITLE: A Reconfigurable Posit Tensor Unit with Variable-Precision Arithmetic and Automatic Data Streaming Full Text
AUTHORS: Neves, N; Tomas, P; Roma, N;
PUBLISHED: 2021, SOURCE: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
AUTHORS: Neves, N; Tomas, P; Roma, N;
PUBLISHED: 2021, SOURCE: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
INDEXED IN: WOS
WOS4
TITLE: Reconfigurable Stream-based Tensor Unit with Variable-Precision Posit Arithmetic Full Text
AUTHORS: Neves, N; Tomas, P; Roma, N;
PUBLISHED: 2020, SOURCE: 31st IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP) in 2020 IEEE 31ST INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2020), VOLUME: 2020-July
AUTHORS: Neves, N; Tomas, P; Roma, N;
PUBLISHED: 2020, SOURCE: 31st IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP) in 2020 IEEE 31ST INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2020), VOLUME: 2020-July
INDEXED IN: Scopus WOS
Scopus WOS5
TITLE: Dynamic Fused Multiply-Accumulate Posit Unit with Variable Exponent Size for Low-Precision DSP Applications Full Text
AUTHORS: Neves, N; Tomas, P; Roma, N;
PUBLISHED: 2020, SOURCE: 34th IEEE Workshop on Signal Processing Systems, SiPS 2020 in IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, VOLUME: 2020-October
AUTHORS: Neves, N; Tomas, P; Roma, N;
PUBLISHED: 2020, SOURCE: 34th IEEE Workshop on Signal Processing Systems, SiPS 2020 in IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, VOLUME: 2020-October
INDEXED IN: Scopus
Scopus6
TITLE: Multicore SIMD ASIP for Next-Generation Sequencing and Alignment Biochip Platforms
AUTHORS: Neves, N; Sebastiao, N; Matos, D; Tomas, P; Flores, P; Roma, N;
PUBLISHED: 2014, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AUTHORS: Neves, N; Sebastiao, N; Matos, D; Tomas, P; Flores, P; Roma, N;
PUBLISHED: 2014, SOURCE: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
INDEXED IN: Scopus
Scopus