Nuno Filipe Simões Santos Moraes Neves
AuthID: R-00J-05P
11
TITLE: Unified Posit/IEEE-754 Vector MAC Unit for Transprecision Computing
AUTHORS: Crespo, Luis; Tomas, Pedro ; Roma, Nuno ; Neves, Nuno;
PUBLISHED: 2022, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, VOLUME: 69, ISSUE: 5
AUTHORS: Crespo, Luis; Tomas, Pedro ; Roma, Nuno ; Neves, Nuno;
PUBLISHED: 2022, SOURCE: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, VOLUME: 69, ISSUE: 5
12
TITLE: Compiling for Vector Extensions With Stream-Based Specialization
AUTHORS: Neves, Nuno; Domingos, Joao Mario; Roma, Nuno ; Tomas, Pedro ; Falcao, Gabriel;
PUBLISHED: 2022, SOURCE: IEEE MICRO, VOLUME: 42, ISSUE: 5
AUTHORS: Neves, Nuno; Domingos, Joao Mario; Roma, Nuno ; Tomas, Pedro ; Falcao, Gabriel;
PUBLISHED: 2022, SOURCE: IEEE MICRO, VOLUME: 42, ISSUE: 5
14
TITLE: HEDAcc: FPGA-based Accelerator for High-order Epistasis Detection Full Text
AUTHORS: Gaspar Ribeiro; Nuno Neves; Sergio Santander Jiménez; Aleksandar Ilic;
PUBLISHED: 2021, SOURCE: FCCM
AUTHORS: Gaspar Ribeiro; Nuno Neves; Sergio Santander Jiménez; Aleksandar Ilic;
PUBLISHED: 2021, SOURCE: FCCM
15
TITLE: Unlimited Vector Extension with Data Streaming Support
AUTHORS: Domingos, JM; Neves, N; Roma, N ; Tomas, P ;
PUBLISHED: 2021, SOURCE: ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA) in 2021 ACM/IEEE 48TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2021), VOLUME: 2021-June
AUTHORS: Domingos, JM; Neves, N; Roma, N ; Tomas, P ;
PUBLISHED: 2021, SOURCE: ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA) in 2021 ACM/IEEE 48TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2021), VOLUME: 2021-June
16
TITLE: A Reconfigurable Posit Tensor Unit with Variable-Precision Arithmetic and Automatic Data Streaming
AUTHORS: Neves, N; Tomas, P ; Roma, N ;
PUBLISHED: 2021, SOURCE: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, VOLUME: 93, ISSUE: 12
AUTHORS: Neves, N; Tomas, P ; Roma, N ;
PUBLISHED: 2021, SOURCE: JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, VOLUME: 93, ISSUE: 12
17
TITLE: HEDAcc: FPGA-based Accelerator for High-order Epistasis Detection
AUTHORS: Gaspar Ribeiro; Nuno Neves; Sergio Santander Jimenez; Aleksandar Ilic;
PUBLISHED: 2021, SOURCE: Proceedings - 29th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2021
AUTHORS: Gaspar Ribeiro; Nuno Neves; Sergio Santander Jimenez; Aleksandar Ilic;
PUBLISHED: 2021, SOURCE: Proceedings - 29th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2021
INDEXED IN: 
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ORCID
ORCID18
TITLE: Reconfigurable Stream-based Tensor Unit with Variable-Precision Posit Arithmetic
AUTHORS: Neves, N; Tomas, P ; Roma, N ;
PUBLISHED: 2020, SOURCE: 31st IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP) in 2020 IEEE 31ST INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2020), VOLUME: 2020-July
AUTHORS: Neves, N; Tomas, P ; Roma, N ;
PUBLISHED: 2020, SOURCE: 31st IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP) in 2020 IEEE 31ST INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 2020), VOLUME: 2020-July
19
TITLE: Dynamic Fused Multiply-Accumulate Posit Unit with Variable Exponent Size for Low-Precision DSP Applications
AUTHORS: Neves, N; Tomas, P; Roma, N ;
PUBLISHED: 2020, SOURCE: 34th IEEE Workshop on Signal Processing Systems, SiPS 2020 in IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, VOLUME: 2020-October
AUTHORS: Neves, N; Tomas, P; Roma, N ;
PUBLISHED: 2020, SOURCE: 34th IEEE Workshop on Signal Processing Systems, SiPS 2020 in IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, VOLUME: 2020-October
