Dft and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In

AuthID
 P-003-8P3
5
Author(s)
Kao, WC
·
Chuang, WS
·
Lin, HT
·
Li, JCM
·
Document Type
Article
Year published
2010
Published
in IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, ISSN: 1063-8210
Volume: 18, Issue: 3, Pages: 392-400 (9)
Indexing
Wos®
Scopus®
Crossref®
Google Scholar®
Publication Identifiers
Scopus: 2-s2.0-77649185652
Wos: WOS:000274995400005
Source Identifiers
ISSN: 1063-8210
Export Publication Metadata
Marked List
 Add to Marked List
Info
At this moment we don't have any links to full text documens.

A place for researchers and their institutions

Useful Links

Get Help

© 2024 CRACS & Inesc TEC - All Rights Reserved Privacy Policy | Terms of Service