A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time Σδ Modulators

AuthID
 P-007-YR7
6
Author(s)
Jiang, Y
·
Wong, KF
·
Cai, CY
·
Sin, SW
·
Document Type
Proceedings Paper
Year published
2010
Published
in IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Pages: 1011-1014
Conference
2010 Asia Pacific Conference on Circuit and System, Apccas 2010, Date: 6 December 2010 through 9 December 2010, Location: Kuala Lumpur
Indexing
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Publication Identifiers
Scopus: 2-s2.0-79959207880
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