Floorplan-Aware Analog Ic Sizing and Optimization Based on Topological Constraints

AuthID
 P-00A-0X7
5
Author(s)
Document Type
Article
Year published
2015
Published
in INTEGRATION-THE VLSI JOURNAL, ISSN: 0167-9260
Volume: 48, Issue: 1, Pages: 183-197 (15)
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Wos®
Scopus®
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Google Scholar®
Publication Identifiers
Scopus: 2-s2.0-85028165436
Wos: WOS:000345541100017
Source Identifiers
ISSN: 0167-9260
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