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A 0.0285Mm2 0.68Pj/Bit Single-Loop Full-Rate Bang-Bang Cdr Without Reference and Separate Frequency Detector Achieving an 8.2(Gb/S)/Μs Acquisition Speed of Pam-4 Data in 28Nm Cmos

AuthID
P-00S-3H0

Author(s)

Zhao, X

Chen, Y

Mak, PI

Martins, RP

Document Type

Proceedings Paper

Year published

2020

Published

in Proceedings of the Custom Integrated Circuits Conference, ISSN: 0886-5930

Volume: 2020-March

Conference

2020 Ieee Custom Integrated Circuits Conference, Cicc 2020, Date: 22 March 2020 through 25 March 2020

Indexing

Scopus^®

Google Scholar^®

Publication Identifiers

DOI: 10.1109/cicc48029.2020.9075885

Scopus: 2-s2.0-85084444667

Source Identifiers

ISSN: 0886-5930

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A 0.0285Mm2 0.68Pj/Bit Single-Loop Full-Rate Bang-Bang Cdr Without Reference and Separate Frequency Detector Achieving an 8.2(Gb/S)/Μs Acquisition Speed of Pam-4 Data in 28Nm Cmos

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A 0.0285Mm2 0.68Pj/Bit Single-Loop Full-Rate Bang-Bang Cdr Without Reference and Separate Frequency Detector Achieving an 8.2(Gb/S)/Μs Acquisition Speed of Pam-4 Data in 28Nm Cmos

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