61
TÍTULO: Cache-Aware Roofline Model and Medical Image Processing Optimizations in GPUs
AUTORES: Estefania Serrano; Aleksandar Ilic; Leonel Sousa; Javier García Blas; Jesús Carretero;
PUBLICAÇÃO: 2018, FONTE: High Performance Computing - ISC High Performance 2018 International Workshops, Frankfurt/Main, Germany, June 28, 2018, Revised Selected Papers, VOLUME: 11203
INDEXADO EM: DBLP
NO MEU: DBLP
62
TÍTULO: Beyond the Roofline: Cache-Aware Power and Energy-Efficiency Modeling for Multi-Cores
AUTORES: Ilic, A; Pratas, F; Sousa, L ;
PUBLICAÇÃO: 2017, FONTE: IEEE TRANSACTIONS ON COMPUTERS, VOLUME: 66, NÚMERO: 1
INDEXADO EM: Scopus WOS DBLP CrossRef: 13
NO MEU: DBLP
63
TÍTULO: GPU Parallelization of HEVC In-Loop Filters
AUTORES: Biao Wang; Diego F de Souza; Mauricio Alvarez Mesa; Chi Ching Chi; Ben H H Juurlink; Aleksandar Ilic; Nuno Roma ; Leonel Sousa ;
PUBLICAÇÃO: 2017, FONTE: International Journal of Parallel Programming, VOLUME: 45, NÚMERO: 6
INDEXADO EM: Scopus DBLP
NO MEU: DBLP
64
TÍTULO: GHEVC: An Efficient HEVC Decoder for Graphics Processing Units  Full Text
AUTORES: Diego F de Souza; Aleksandar Ilic; Nuno Roma ; Leonel Sousa ;
PUBLICAÇÃO: 2017, FONTE: IEEE TRANSACTIONS ON MULTIMEDIA, VOLUME: 19, NÚMERO: 3
INDEXADO EM: Scopus WOS DBLP CrossRef
NO MEU: DBLP
65
TÍTULO: Energy-aware mechanism for stencil-based MPDATA algorithm with constraints
AUTORES: Rojek, K; Ilic, A; Wyrzykowski, R; Sousa, L ;
PUBLICAÇÃO: 2017, FONTE: CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, VOLUME: 29, NÚMERO: 8
INDEXADO EM: Scopus WOS DBLP CrossRef: 10
NO MEU: DBLP
66
TÍTULO: Accelerating the phylogenetic parsimony function on heterogeneous systems
AUTORES: Sergio Santander Jiménez; Aleksandar Ilic; Leonel Sousa ; Miguel A Vega Rodríguez;
PUBLICAÇÃO: 2017, FONTE: Concurrency and Computation: Practice and Experience, VOLUME: 29, NÚMERO: 8
INDEXADO EM: Scopus DBLP CrossRef: 3
NO MEU: DBLP
67
TÍTULO: On Boosting Energy-Efficiency of Heterogeneous Embedded Systems via Game Theory
AUTORES: David Pereira; Aleksandar Ilic; Leonel Sousa ;
PUBLICAÇÃO: 2017, FONTE: 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 6th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2017 in Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017, VOLUME: Part F126743
INDEXADO EM: Scopus DBLP CrossRef: 1
NO MEU: DBLP
68
TÍTULO: Exploring GPU performance, power and energy-efficiency bounds with Cache-aware Roofline Modeling
AUTORES: Andre Lopes; Frederico Pratas; Leonel Sousa ; Aleksandar Ilic;
PUBLICAÇÃO: 2017, FONTE: 2017 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2017, Santa Rosa, CA, USA, April 24-25, 2017
INDEXADO EM: Scopus DBLP CrossRef: 28
NO MEU: DBLP
69
TÍTULO: Cache-aware Roofline Model in Intel® Advisor
AUTORES: Leonel Sousa; Aleksandar Ilic;
PUBLICAÇÃO: 2017, FONTE: ERCIM News, VOLUME: 2017, NÚMERO: 110
INDEXADO EM: DBLP
NO MEU: DBLP
70
TÍTULO: Performance Analysis with Cache-Aware Roofline Model in Intel Advisor
AUTORES: Diogo Marques; Helder Duarte; Aleksandar Ilic; Leonel Sousa; Roman Belenov; Philippe Thierry; Zakhar A Matveev;
PUBLICAÇÃO: 2017, FONTE: 2017 International Conference on High Performance Computing & Simulation, HPCS 2017, Genoa, Italy, July 17-21, 2017
INDEXADO EM: DBLP
NO MEU: DBLP
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