41
TÍTULO: FPGA Redundancy Recovery based on Partial Bitstreams for Multiple Partitions
AUTORES: Victor M G Goncalves Martins; Joao Gabriel Reis; Horacio C C Neto; Eduardo Augusto Bezerra;
PUBLICAÇÃO: 2015, FONTE: 16th IEEE Latin American Test Symposium (LATS) in 2015 16TH LATIN-AMERICAN TEST SYMPOSIUM (LATS)
INDEXADO EM: WOS
42
TÍTULO: Enhancing Stochastic Computations via Process Variation
AUTORES: Rui Policarpo Duarte; Mario Vestias; Horacio Neto;
PUBLICAÇÃO: 2015, FONTE: 25th International Conference on Field Programmable Logic and Applications in 2015 25TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS
INDEXADO EM: WOS
43
TÍTULO: Efficient implementation of a single-precision floating-point arithmetic unit on FPGA
AUTORES: Jose, W; Silva, AR; Neto, H; Vestias, M;
PUBLICAÇÃO: 2014, FONTE: 24th International Conference on Field Programmable Logic and Applications, FPL 2014 in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
INDEXADO EM: Scopus CrossRef Handle
NO MEU: ORCID
44
TÍTULO: Trends of CPU, GPU and FPGA for high-performance computing
AUTORES: Vestias, M; Neto, H;
PUBLICAÇÃO: 2014, FONTE: 24th International Conference on Field Programmable Logic and Applications, FPL 2014 in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
INDEXADO EM: Scopus CrossRef
NO MEU: ORCID
45
TÍTULO: Modeling and Simulation of a Many-Core Architecture Using SystemC
AUTORES: Ana Rita Silva; Wilson Jose; Horacio Neto; Mario Vestias;
PUBLICAÇÃO: 2014, FONTE: 2nd Conference on Electronics, Telecommunications, and Computers (CETC) in CONFERENCE ON ELECTRONICS, TELECOMMUNICATIONS AND COMPUTERS - CETC 2013, VOLUME: 17
INDEXADO EM: WOS CrossRef
46
TÍTULO: Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication
AUTORES: Wilson M José; Ana Rita Silva; Mário P Véstias; Horácio C Neto;
PUBLICAÇÃO: 2014, FONTE: Analog Integrated Circuits and Signal Processing - Analog Integr Circ Sig Process, VOLUME: 82, NÚMERO: 1
INDEXADO EM: CrossRef Handle
NO MEU: ORCID
47
TÍTULO: Very low resource table-based FPGA evaluation of elementary functions
AUTORES: Neto, HC; Vestias, MP;
PUBLICAÇÃO: 2013, FONTE: 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013 in 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013
INDEXADO EM: Scopus CrossRef
NO MEU: ORCID
48
TÍTULO: Analysis of matrix multiplication on high density Virtex-7 FPGA
AUTORES: Jose, W; Silva, AR; Neto, H; Vestias, M;
PUBLICAÇÃO: 2013, FONTE: 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 in 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
INDEXADO EM: Scopus CrossRef
NO MEU: ORCID
49
TÍTULO: A reconfigurable computing architecture using magnetic tunneling junction memories
AUTORES: Silva, V; Fernandes, J; Vestias, M; Neto, H;
PUBLICAÇÃO: 2013, FONTE: 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 in 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
INDEXADO EM: Scopus CrossRef
NO MEU: ORCID
50
TÍTULO: Decimal division using the newton-raphson method and radix-1000 arithmetic
AUTORES: Vestias, MP; Neto, HC;
PUBLICAÇÃO: 2013, FONTE: Embedded Systems Design with FPGAs
INDEXADO EM: Scopus
NO MEU: ORCID
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